in~.
HARDWARE DESCRIPTIONOF THE 8051,8052 AND 80C51
Table4.EPROMVersionsofthe8051and8052
Device EPROM EPROM
Ckt
VPP
Time Required to
Name
Version
Bytes
Type
ProgramEntireArray
8051AH 8751H/8751BH 4K
HMOS
21.0V112.75V
4 minutes
80C51BH 87C51
4K CHMOS
12.75V
13 seconds
1
8052AH 8752BH 8K
HMOS 12.75V 26 seconds
tions are stopped, but the on-chipRAM and Special
FunctionRegisteraare held. The port pins output the
valuesheld by their reapecdveSFRS.ALE and P8EN
output lows.
The only exit from Power Down for the 80C51is a
hardwarereset. Reset redefinesall the SPRS,but does
not changethe on-chipW.
In the Power Down mode of operation,VCC can be
reducedto as lowas 2V.Care mustbe taken,however,
to ensure that VCC is not reduced beforethe Power
Downmodeis invoked,and that VCCis restoredto its
normaloperatinglevel,beforethe PowerDownmodeis
terminated.Thereset that terminatesPowerDownalso
frees the oaeillator.The reset shouldnot be activated
before VCC is restored to its normal operatinglevel,
and mustbeheld active longenoughto allowthe oscil-
lator to restart and stabilise (normally less than 10
maec).
EPROMVERSIONS
TheEPROMversionsof thesedevieesare listedin Ta-
ble 4. The 8751Hprograms at VPP = 21Vusingone
50 msec PROO pulse per byte programmed.This re-
sultsin a total programmingtime(4Kbytes)ofapprox-
imately4 minutes.
The 8751BH, 8752BH and 87C51 use the faster
‘@i~k-p~>>
pro~gm ~gorithm. ~= de-
12.75Vusing a series of
twenty-fiveIMlps PROOpulsesper byteprogrammed.
This results in a total programmingtime of approxi-
mately 26 seconds for the 8752BH(8 Kbytes) and
13seeondsfor the 87C51(4
Kbytes).
Detailedprocedures for pro
gramming and verifying
each deviceare givenin the data sheets.
Exposureto Light
It is good practice to cover the EPROM windowwith
an opaquelabelwhenthe deviceis in operation.Thisis
not so much to protect the EPROM array from inad-
vertenterssure but to protect the RAM and other on-
chiplogic.Allowinglight to impingeon the silicondie
whilethe deviceis operatingcancsuaelogicalmalfhne-
tion.
ProgramMemoryLocks
In somemicrocontrollerapplicationsit is desirablethat
the Program Memorybe securefrom softwarepiracy.
Intel has respondedto this need by implementinga
ProgramMemorylockingschemein someofthe MCS-
51devices.Whileit is impossiblefor anyoneto guaran-
tee absolutesecurityagainatall levelsof technological
sophistication,the ProgramMemorylocksin the MCS-
51deviceswillpresenta substantialbarrier againatille-
gal readoutof proteetedsoftware.
One Lock Bit Scheme on 8751H
The
8751H contains a lock bit which, once pro-
grammed, denies electrical access by any external
meansto the on-chipProgramMemory.The etht of
this lockbit is that whileit is programmedthe internal
Program Memorycan not be read out, the devicecan
not be further programmed,and it
can not execute ex-
ternal ?%ognamMemory.
Erasing the EPROM array
deactivatesthe lock bit and restores the device’sfull
functionality.It can thenbe re-progratnmed.
Theprocedureforprogrammingthe lockbit is detailed
in the 8751Hdata sheet.
Two ProgramMemoryLockSshemes
The8751BH,8752BHand 87C51containtwoProgram
Memorylockingschemes:Encryptedverify and Lock
Bits.
EncryptionArraw Withinthe EPROM is an array of
encryptionbytes that are initiallyunprogrammCd(au
l’s). The user ean program the array to encrypt the
code bytes during EPROM veriftcstion.The verifica-
tion procedure sequentiallyXNORS each code byte
withoneofthe keybytes.Whenthe last keybytein the
-Y k reached,the verifyroutinestarts overwith the
first byteofthe array forthe nextcodebyte. If the key
byteaare unprogrammed,the XNORprocess
leavesthe
codebyteunchanged.Withthe keybytesprogrammed,
the codebytesare encryptedand can be read correctly
only if the key bytesare knownin their proper order.
Table 6 lists the numberof encryptionbytrs available
on the variousproducts.
Whenusingthe encryptionarray, one important factor
should be considered.If a code byte has the value
3-29
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