in~.
8XC52/54/55 HARDWARE DESCRIPTION
Table 7. Priority Level Bit Values
11101
Level2
I
11111
Level3 (Hiahest)
I
POWER DOWN MODE
The 8XC5X can exit Power Down with either a hard-
ware reaetor external interrupt.Reset redefinesall the
SFRSbut deeanot change the
on-chiD RAM. An exter-
nal interrupt allows ~th the SF& (except PD in
PCON) and the on-chip RAM to retairstheir values
‘*
Figure 6. Interrupt Bources
To properlyterminate Power Down the reset or exter-
nal interrupt should not be applied before VCC is re-
stored to its normal operating level and must be held
active long enough for the oscillatorto reatartand sta-
bilize (normally leas than 10 msec).
With an external interrupt, ~ or ~ must be en-
abled and configured as level-sensitive before entering
Power Down. Holding the pin low restartsthe Oscilla-
tor and bringing the pin back high completes the exit.
After the RETI instruction is executedin the interrupt
seMce routin%the next instruction will be the one fol-
lowing the instruction that put the device in Pow=
Down.
POWER OFF FLAG
The
Power Off Flag (POF) located at PCON.4 is set by
hardwarewhen VCCrises from Oto approximately5V.
POF can also be set or clearedby software.This allows
the user to distinguish between a “cold start” reset and
a “warmstart” reset.
A cold start reaet is one that is coincident with Vcc
being turned onto the device afterit was turned off. A
warmstartreset occurs while VCCis still applied to the
device and could be generated, for example, by an exit
from Power Down.
Immediately after reset, the usefs softwarecan check
the status of the POF bit. POF = 1 would indicate a
cold start. The software then clears POF and com-
mences ita tasks. POF = O immediately after reset
would indieete a warm start.
Vcc must remain above 3V for POF to retain a O.
Program Memory Lock
In
some microcontrollerapplicationsit is desirable that
the Program Memory be secure from software piracy.
The 8XC5X has varyingdegreesof programprotection
depending on the device. Table 8 outlines the lock
schemes available for each device.
EncryptionArray:Within the EPROM/ROM is sssar-
rayof encryptionbytes that areinitiallyunprogrammed
(sU l’s). For EPROM devices, the user can program
the encryptionarrayto encrypt the programcode bytes
during EPROM veritktion. For ROM devices, the
risersubmits the encryption arrayto be programmedby
the factory. If an encryption arrayis submitted, LB1
will also beprograrnrnedby the factory.The encryption
array is not available without the Lock Bit. Program
cmle verificationis petformed as usualexcept that each
code byte comes out exclusive-NOR’ed ~NOR) with
one of the key bytes. Therefore, to read the
ROIWEPROM cede, the user has to know the encryp-
tion key bytes in their proper sequence.
Unprogrammedbytes have the value OFFH. If the En-
cryption Array is left unprogrammed,all the key bytes
have the value OFFH. Since any code byte XNOR’ed
4-12
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