i~.
8XC51FXHARDWAREDESCRIPTION
CH is incremented after two oscillator periods when
The CCON register,shown in Table 11, contains two
CL OVdOWS.
more bits which are
associated with the PCA timer/
counter. The CF bit gets set by hardwme when the
The mode register CMOD contains the Count Puke counter overtlows, and the CR bit is set or clearedto
8elect bits (C%l and CPSO)to specify the clock input. turn the counter on or off. The other five bits in this
CMOD is shown in Table 10. This registeralso eon-
register are the event figs for the compare/capture
tains the ECF bit which enablesthe PCA counterover-
moduks and will be diseuaaedin the next section.
flow to generate the PCA
interrupt. In addition, the
user
has the option of turning off the PCA timerduring
Idle Mode by setting the Counter Idle bit (CIDL). The
Watchdog Timer Enable bit (WDTE) will be diaoussed
in a later section.
Table 10. CMOD:PCA Counter Mode Register
CMOD
Address= OD9H
ResetValue= OOXXXOOOB
Not Bit Addressable
CIDL WDTE
— — —
CPS1
CPSO
ECF
Bit
7 6 5
4
3 2
1
0
SYmbol Function
CIDL CounterIdlecontrol:CIDL= OprogramsthePCACountertocontinuefunctioningduring
idleMode.CIDL= 1programsit to begatedoffduringidle.
WDTE WatchdogTimerEnable:WDTE= OdiaeblesWatchdogTimerfunctiononPCAModule4.
WDTE= 1enablesit.
—
Notimplemented,resewedforfutureuse.*
CPS1
PCACountPuleeSelectbit1.
CPSO
PCACountPulseSelectbitO.
CPS1 CPSO Selected PCAInput**
o
0 Internalclock,Fosc+ 12
0 1 Internalclock,FOSC+4
1
0
TimerOoverflow
1 1 External
clockat ECVP1.2pin(max.rate= Fosc+8)
ECF
PCAEnableCounterOverflowinterruptECF= 1enablesCFbitinCCONto generatean
interrupt.ECF= OdisablesthatfunctionofCF.
NOTE
*UaersoftwareshouldnotwritsIs toraaerved
bik.ThSSSbitsmaybeused
infutureS051 familyproduetato invoke
newfeaturea.
In that ease, the reset or inaetkfe value of the new bit will be O, and ifs active value will be 1. The value
read from a reaerved bit is indeterminate.
●*FOSC = oscillator frequeney
5-21
To Next Page
Loading...
Need help?
General
