in~.
8XC51FXHARDWAREDESCRIPTION
8.1 External lnterrupta
External
Interrupts~ and INT1 can each be either
level-activated or transition-activated, depending on
bits ITOand IT1 in registerTCON. If ITx = O,exter-
nal interrupt x is triggered by a detected low at the
~ pin. If ITx = 1, external intemupt x is negative
edge-triggered.The flags that actually generate these
interruptsare bits IEOand IEl in TCON. These flags
are cleared by hardware when the service routine is
vectoredto only if the interruptwas tranaition-aetivat-
ed. If the interruptwas Ievel-aetivatq then the exter-
md requesting source is what controls the request tlag,
ratherthantheon-chiphardware.
Since the externalinterruptpins aresampled once each
machine cycle an input high or low should hold for at
least 12 oscillator perioda to ensure sampling. If the
external interrupt is transition-activated, the external
sourcz has to hold the request pin high for at least one
cycle, and then hold it low for at least one cycle to
ensure that the transition is seen so that interrupt re-
quest flag IEx will be set. IEx will be automatically
clearedby the CPU when the seMce routine is called.
If external interrupt~ or ~ is level-activat~
the externalsource has to hold the request active until
the requested interrupt is actually generated. Then it
has to deactivatethe requestbefore the interrupt serv-
ice routine is completed, or else another interruptwill
be generated.
8.2 Timer Interrupts
Timer Oand Timer 1 Interrupts are generatedby TFO
and TFl in registerTCON, which are set by a rollover
in their respectiveTimer/Counter registers(except see
Timer Oin Mode 3). When a timer interruptis generat-
ed, the tlag that generated it is cleared by the on-chip
hardwarewhen the service routine is vectored to.
Timer 2 Interruptis generatedby the logical OR of bits
TF2 and EXF2 in register T2CON. Neither of these
tlags is clearedby hardwarewhen the serviceroutine is
vectored to. In f- the service routine may have to
determinewhetlm it was TF2 or EXF2 that generated
the interrupt, and the bit will have to be cleared in
software.
8.3 PCA Interrupt
The PCA interrupt is generated by the logical OR of
CF, CCFO,CCFI, CCFZ,CCF3, and CCF4 in register
CCON. None of these flags is cleared by hardware
when the service routine is vectored to. Normally the
service routinewill have to determine which bit flagged
the interrupt and ckar that bit in software. The PCA
interrupt is enabled by bit EC in the InterruptEnable
register (see Table 16). In addition, the CF flag and
each of the CCFn flags must also be enabled by bits
ECF and ECCFn in registers CMOD and CCAPMn
respectively,in orderfor that flag to be able to causean
interrupt.
8.4 Serial Port Interrupt
The serirdport interruptis generatedby the logical OR
of bits RI and TI in register SCON. Neither of these
tlags is clearedby hardwarewhen the service routineis
vectored to. The seMee routine will normally have to
determine whether it was RI or ‘H that generatedthe
interrupt, and the bit will have to be cleared in sotl-
ware.
8.5 Interrupt Enable
Each of these interruptsources can be individually en-
abled or disabled by setting or clearing a bit in the
Interrupt Enable (fE) register. (See Table 17.) Note
that IE also contains a global disable bit, EA. If EA is
set (1), the interrupts are individually enabled or dis-
abled by their correspondingbits in IE. If EA is clear
(0), all interrupts are disabled.
8.6 Priority Level Structure
Each interrupt source can also be individually pro-
_ed to one of two priority levels, by
settingor
clearing a bit in the Intemupt Priority (1P) register
shown in Table 18. A low-priority interrupt can itself
be interruptedby a higherpriorityinterrupt,but not by
another low-priority interrupt. A high priority inter-
rupt
CSIUIOt be interrupted by my Other interrupt
source.
5-33
To Next Page
Loading...
Need help?
General
