Intel MCS 51 User Manual

i~. M=@-51 PROGRAMMER’SGUIDEAND INSTRUCTION SET
ThoseSFRsthat havetheirbits assignedforvariousfunctionsare listedin this section.A briefdescriptionofeachbit
is providedfor quickreference.For moredetailedinformationrefer to the Architecture Chapterof this book.
PSW: PROGRAM STATUS WORD. BIT ADDRESSABLE.
CY
AC FO RS1
RSO Ov I — I P
CY
PSW.7
Carry
Flag.
AC
PSW.6
AuxiliaryCarry Flag,
FO
PSW.5 Flag Oavailableto the user for generalpurpose.
Rsl
PSW.4
RegisterBankselectorbit 1(SEENOTE 1).
Rso
PSW.3 RegisterBankselectorbit O(SEENOTE 1).
Ov
PSW.2
OverflowFlag.
—
Psw.1
Userdefinableflag.
P
Psw.o Parityflag.Set/clearedby herdwareeachinstructioncycleto indicateerrodd/werrnumberof
‘1’bitain the accumulator.
NOTE:
1.ThevaluepresentedbyRSOandRS1selectsthecorrespondingregisterbank.
RS1
RSO Register Bank Address
o
0 0 OOH-07H
o 1 1 08H-OFH
1
0
2 10H-17H
1 1
3
18H-l FH
PCON: POWER CONTROL REGISTER. NOT BIT ADDRESSABLE.
SMOD I — I — I — GF1
GFO PD IDL
SMOD Doublebaudrate bit. If Timer 1 is used to generatebaud rate end SMOD = 1,the baudrate is doubled
whenthe SeriatPort is used in modes1,2, or 3.
—
Not implemented,reservedfor future w.*
—
Not implemented,reservedfor future w.*
—
Not implemented,r
eservedfor future use.”
GF1
Generalpurposeflagbit.
GFO Generalpurposeflagbit.
PD
Power Downbit. Setting this bit activates Power Down operation in the 80C51BH.(Availableonly in
CHMOS).
IDL
Idle Modebit. %.ttittgthis bit activatesIdle Modeoperationin the 80C51BH.(Availableonlyin CHMOS).
If 1sarewrittento PDandIDLat thesametimejPDtske$precedence,
●Usersoftwareshouldnotwrite1s to reservedbita.Thaeebitsmaybe usedin futureMCS-51productsto invokenew
featurea.Inthatcase,theresetorinactivevalueofthenewbitwillbeO,anditsectivevaluewillbe1.
2-11

Intel MCS 51 Specifications

General

Brand	Intel
Model	MCS 51
Category	Microcontrollers
Language	English