i~.
83C152 HARDWARE DESCRIPTION
TSTAT.1(TEN)- Transmit Enable- Whenset causes
TDN, UR, TCDT, and NOACK flag to be reset and
the TFIFO cleared.The
transmitter willclearTEN sf-
ter a successfultransmission, a collision during the
data,CRC or endtlag.Theusersoftwareis responsible
forsettingbut the GSCor user softwaremayclearthis
flag.If clearedduringa transmissionthe GSCtransmit
pingoesto a steadystate highlevel.This is the method
usedto aendan abortcharacter in SDLC.Also~ is
forcedto a highlevel.The end of transmissionoccurs
wheneverthe TFIFO is emptied.
TSTAT.2(TFNF) - T
ransmit FIFO not full - When
set, indicates that new data may be written into the
transmitFIFO. Thetransmit FIFO is a threebytebuff-
er that loadsthe transmit shift registerwith data. The
status of this flagis controlledby the GSC.
TSTAT.3(TDN) - Transmit Done - When seL indi-
catesthe successfulcompletionofa frametransmission.
If HABENis set, TDN willnot be set until the end of
the IFS followingthe transmitted measage,so that the
acknowledgecan be checked.If an acknowledgeis ex-
pectedand not roxived, TDN is not set. An acknowl-
edgeis notexpectedfollowinga broadcastor multi-cast
packet.Thestatus ofthis ilagis controlledbythe GSC.
TSTAT.4(TCDT)- Transmit CollisionDetect -If seL
indicatesthat the transmitter halted due to a collision.
It is set ifa collisionoccursduringthe data or CRCor
ifthereare morethan eightcollisions.Thestatusofthis
tlag is controlledby the GSC.
TSTAT.5(U’R)- Underrun - If set, indicatesthat in
DMAmodethe lastbit wasshiftedout of the transmit
register ~d that the DMA byte count did
not equal
zero. When an
underrunoccurs,the transmitterhalts
withoutsendingthe CRC or the endflag.Thestatusof
this flagis controlledby the GSC.
TSTAT.6(NOACK)- No Acknowledge- If set, indi-
catesthat noacknowledgewasreceivedforthe previous
frame. Will be set only if HABEN is set and no ac-
knowledgeis received prior to the end of the IFS.
NOACK is not set followinga broadcast or a multi-
cast packet.The status of this tlag is controUedby the
GSC.
TSTAT.7(LNI) - Line Idle - If set, indicatesthe re-
ceivelineisidle.In SDLCprotccolit isset if 15consec-
utive one are received.In CSMA/CD protocol,line
idleisset ifGRXD remainshighfor approximately1.6
bit times.LNI is clearedafter a transitionon GRXD.
The status of this flagis controlledby the GSC.
3.8 SerialBackplanevs.Network
Environment
The C152GSCportis intended to fidfii the needsof
both serialbackplaneenvironmentand the serial com-
municationnetworkenvironment.The serialbackplane
is wheretypically,onlypr
ocesaorto pmxaaor commu-
nicationstake place within a self containedbox. The
communicationusually only encompassesthose items
whichare necewary
to accomplishthe dedicatedtask
forthe box.In thesetypesofapplicationstheremaynot
be a need for line drivers as the distancebetweenthe
transmitter and receiver is relatively short. The net-
workenvironment;however,usuallyrequirestransmis-
sion of &ta over large distances and requires drivers
and/or repeatersto ensurethe data is receivedon both
ends.
4.0 DMA Operation
The C152containsDMA (Direct MemoryAccessing)
logicto performhighspeeddata transfersbetweenany
two of
Internal Data RAM
Internal SFRS
ExternrdData RAM
If externalRAMis involved,the Port 2and Port O~
are used as the addreaa/data bus, and ~ and WR
signalsare generatedas required.
Hardwareis also implementedto generatea HoldRe-
queat signaland await a Hold Acknowledgeresponse
before commencinga DMA that involves external
RAM.
Alternatively,the Hold/Hold Acknowledgehardware
grammedto accept a Hold Request signal
can be pro
froman externrddeviceand generatea Hold Acknowl-
edge signrdin response,to indicate to the requesting
devicethat the C152willnot commencea DMA to or
from externalRAM whilethe Hold Requestis active.
4.1
DMAwith the 80C152
The C152containstwoidenticalgeneralpurpose8-bit
DMA charmekwith 16-bitaddreasability:DMAOand
DMA1.DMAtransferscanbeexecutedbyeither
Chann-
el independentofthe other,but onlybyonechannelat
a time. Duringthe time that a DMA transfer is being
executed, program execution is suspended.A DMA
transfer takes one machine cycle
(12 oscillator
7-47
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