in~.
HARDWARE DESCRIPTION OFTHE 8051,8052 AND 80C51
As data bita shiftout to the right,zeroesare clockedin
fromthe left. Whenthe MSBof the data byte is at the
outputpositionofthe shift register,then the 1that was
initiallyloadedintothe 9thpositionisjust to the leftof
the MSB,and all positionsto the left of that contain
zeroes.This conditiontlags the TX Control unit to do
one last shift and then deactivate SEND and set TI.
This occurs at the loth divide-by-16rollover after
“write to SBUF.”
Receptionis initiatedby a detected l-to-Otransition at
RXD. For this purposeRXD is sampledat a rate of 16
timeswhateverbaudrate has beenestablished.Whena
transitionisdetected,the divide-by-16counteris immed-
iately reaet, and IFFH is written into the input shift
register. Reaettingthe divide-by-16counter aligns its
rolloverswiththe boundariesofthe incomingbit titnea.
The 16states of the counter divideeach bit time into
16ths.At the 7th, 8th,and 9th counterstates ofeachbit
time, the bit detector sampleathe value of RXD. The
value
acceptedisthevaluethat wasseenin at least 2of
the 3 samples.This is done for noise rejection. If the
value accepted during the first bit time is not O,the
receivecircuitsare reset and the unit goeaback to look-
ingfor another l-to-Otransition.This is to providere-
jection offalsestart bita.If the start bit provesvalid,it
is shiftedinto the input shift register,and receptionof
the rest of the thrne willproceed.
As data bits comein fromthe right, 1sshift out to the
left. Whenthe start bit arrives at the leftmost position
in the shift register,(whichin mode 1 is a 9-bit regis-
ter), it figs the RX Controlblock to do onelast shift,
load SBUF and RB8, and set RL The signal to led
SBUFand RB8,and to set RI, willbegeneratedif, and
onlyif, the followingconditionsare met at the timethe
finalshifl pulse is generat.d
1)
RI = O, and
2) EitherSM2 = O,orthereceivedstopbit= 1
If eitherofthesetwoconditionsis notmet, the received
frame is irretrievablylost. If both conditionsare met,
the stop bit goes into RB8, the 8 data bits go into
SBUF,and RI is activated.At this time, whether the
aboveconditionsaremet or not, the unit goesbsek to
lookingfor a l-to-Otransitionin RXD.
MoreAboutModes2 and3
Elevenbitaare transmitted(throughTXD), or received
(throughRXD): a start bit (0),8 data bits (LSBfit), a
programmable9thdata bit, and a stopbit (l). Ontrans-
mit,the 9th data bit (TB8)can be assignedthe valueof
Oor 1.On receivejthe 9th data bit goesinto RB8 in
SCON.Thebaudrate is pro
grammabletoeither Y&or
%. the oscillatorfrequencyin Mcde2. Mode3 may
havea variablebaudrate generatedfromeitherTimer 1
or 2 dependingon the state of TCLK and RCLK.
Figurca 19 and 20 show a fictional diagram of the
serial port in Modes 2 and 3. The receiveportion is
exactlythe same as in Mode 1. The transmit portion
differsfrom Mode 1onlyin the 9th bit ofthe transmit
shiftregister.
Transmissionis initiated by any instructionthat uses
SBUFas a destinationregister.The “write to SBUF”
signalalso bads TB8 into the 9th bit positionof the
transmit shift register and flags the TX Control unit
that a transmiasion is requested. Transmissioncom-
mencesat SIP1ofthe machinecyclefollowingthe next
rollover in the divide-by-16counter. (Thus, the bit
timesare synchronizedto thedivide-by-16counter,not
to the “write to SBUF”signal.)
The transmission begins with activation of SEND,
whichputs the start bit at TXD. One bit time later,
DATAis activated,whichenablesthe outputbit ofthe
transmitshift registerto TXD. The first shitl pulseoc-
curs one bit time after that. The first shift clocks a 1
(thestopbit) intothe 9th bit positionofthe W regis-
ter. Thereafter, ordy seroes are clockedin. Thus, as
data bits shift out to the right, zeroes are clockedin
fromthe left. WhenTB8is at the outputpositionofthe
shitl register,thenthe stopbit isjust to the left ofTB8,
andall positionsto the left of that containzeroes.This
conditionflagsthe TX Controlunit to doonelast shift
and then deactivateSEND and set TL This occurs at
the llth divide-by-16rolloverafter “writeto SBUF.”
Receptionis initiatedbya detected 1-W3transition at
RXD.For this purposeRXD issampledat a rate of 16
timeswhateverbaud rate has beenestablished.Whena
transitionis detect~ thedivide-by-16counteris immed-
iately reaet, and lFFH is written to the input shift
register.
At the 7th, 8tb and 9th counterststes ofeachbit time
the bit detector samplesthe vrdueof RXD. The value
acceptedis the valuethat wasseenin at least2 ofthe 3
samplea.If the valueacceptedduringthe first bit time
is
notO,thereceivecircuitsareresetandtheunitgoes
back to looking for another l-to-Otransition. If the
start bit proveavalid, it is shiftedinto the input shift
register,and receptionofthe rest of the framewillpro-
eecd.
3-20
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