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Intel MCS 51 User Manual

Intel MCS 51
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in~.
HARDWARE DESCRIPTIONOF THE 8051,8052 AND 80C51
Thebaud rate generatormodeissimilarto the auto-re-
loadmcde,inthat a rolloverin TH2causestheTimer2
registerstObereloadedwiththe Id-bitvahseinregisters
RCAP2Hand RCAP2L,whichare presetbysoftware.
Now,the baudrates in Modes 1and 3 are determined
by Timer2’soverflowrate as follows:
Timer2
@clfiow Rate
Modes1,3 BaudRate =
16
The Tim= can be configuredfor either “timer” or
“counter”operation.In the mosttypicalapplications,it
isconfiguredfor “timer” operation(C/T2 = O).“Tim-
er” operationis a fittle differentfor Timer 2 whenit’s
being used as a baud rate generator. Normally,as a
timer it wouldincrementeverymachinecycle(thus at
Y,, the
mdlator frequency).Asa baudrate generator,
however,it incrementseverystate time (thusat ~, the
oscillatorfrequency).In that casethe baudrate is given
by the formula
Mcdes 1,3
OscillatorFrequency
‘aud ‘te = 32x[65536 (RCAP2H,RCAP2L)1
where (RCAP2H, RCAF2L) is the content of
RCAP2Hand RCAP2Ltaken as a Id-bit unsignedin-
teger.
Timer2as a baudrate generatoris showninFigure16.
This Figureis valid only if RCLK + TCLK = 1 in
T2CON.Notethat a rolloverin TH2 doesnot set TP2,
andwillnotgeneratean interrupt.Therefore,theTimer
2 interrupt doesnot have to be disabledwhenTimer 2
is in the baud rate generator mode. Note too, that if
EXEN2 is set, a l-to-O transition in T2EX will set
EXF2 but will not cause a reload from (RCAP2H,
RCAP2L)to (TH2,TL2).ThuswhenTimer2 is in use
as a baudrate generator,T2EX can be usedas an extra
externalinterrupt,if desired.
It shouldbe notedthat whenTimer 2 is
running(TR2
= 1) in “timer” function in the baud rate generator
mod~ oneshouldnot try to read or writeTH2or TL2.
Undertheseconditionsthe Timer is beingincremented
everystate time,and the results of a read or writemay
notbe accurate.The RCAP rcgistm
maybe read, but
shouldn’tbewrittento,becausea writemightoverlapa
reloadand causewrite and/or reload errors. Turn the
Timer off(clearTR2) before
ruessing the Timer2 or
RCAP registers,in this case.
MoreAboutModeO
Serialdata
enters and exits through RXD. TXD out-
puts the shifl clock. 8 bits are tranarnitted/received:8
data bits (LSBfwst).The baud rate is fixedat !/,2the
oscillatorfrequency.
Figure 17showsa simplifiedfunctioneddiagramofthe
serialport in ModeO,and associatedtiming.
Trsnamissionis initiated by any instructionthat uses
SBUFas a destinationregister.The “write to SBUF’
signalat S6P2alsoloadsa 1intothe 9thpositionofthe
transmit shiftregisterand tellsthe TX Controlblockto
commencea tr
ansmission.The internal timingis such
that one till machinecyclewill elapsebetween“write
to SBUF,”and activationof SEND.
SEND enablesthe output of the shift register to the
alternate outputfunctionline of P3.0, and sdsoenables
SHIFf CLOCKto the alternate outputfunctionlineof
P3.1.SHIPT CLOCKis
low during S3,S4,and S5of
everymachinecycle,and highduringS6,S1and S2.At
S6P2of everymachinecyclein whichSENDis active,
the contentsof the transmit shift registerare shiftedto
the right oneposition.
As data bits shift out to the right, zeroescomein from
the left.Whenthe MSBofthe data byteis at theoutput
positionofthe shiftregister,then the 1that wasinitial-
Iyloadedinto the 9th position,isjust to the leftofthe
MSB,andall positionsto the leftofthat containzeroes
This conditionflagsthe TX Control blockto do one
last shitland thendeactivateSENDandsetTL Bothof
these actionsoccur at SIP1 of the loth machinecycle
after “write to SBUF.”
Receptionis initiatedby the conditionREN = 1and
R1 = O.At S6P2of the next machine cyclq the RX
Control unit writes the bits 11111110to the receive
shiftregister,and in the next clockphaseactivatesRE-
CEIVE.
RECEIVE enablesSHIFT CLOCK to the alterstate
output function line of P3.1. SHIIW
CLOCK makes
transitions at S3P1and S6P1of every machinecycle.
At S6P2of everymachinecyclein whichRECEIVEis
active,the contentsofthe receiveshiftregisterare shift-
ed to the left one position. The value that comes in
fromthe right is the vrduethat wassampledat the P3.O
pin at S5P2of the samemachinecycle.
As &ta bits comein from the righL 1sshiftout to the
left.Whenthe Othat wasinitiallyloadedintothe right-
mostpositionarrivesat the leftmostpositionintheshift
register, it flagsthe RX Control block to do one last
shift and load SBUF. At SIP1 of the Klth machine
cycle after the write to SCON that cleared RI, RE-
CEIVEis clearedand RI is set.
MoreAboutMode1
Ten bits are transmitted (through TXD), or received
(through RXD):a start bit (0), 8 data bits (LSBtirst),
and a stop bit (l). on receive,the stop bit gces into
RBgin SCON.In the 8051the baud rate is determined
by the Timer 1 overflowrate. In the 8052it is deter-
minedeitherbythe Timer 1overtlowratejor the Timer
2 overtlowrate or both(onefor transmit and the other
for receive).
Figure 18showsa simplitlsdfunctionaldiagramofthe
serialport in Mode 1,and
associatedtimingsfor trsns-
mit receive.
3-17

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Intel MCS 51 Specifications

General IconGeneral
BrandIntel
ModelMCS 51
CategoryMicrocontrollers
LanguageEnglish

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