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M~@.51 ARCHITECTURAL OVERVIEW
INTRODUCTION
The
8051 is the original member of the MCW-51 family, and is the core for allMCS-51 devices. The features of the
8051 core are -
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8-bit CPU optimized for control applications
Extensive Boolean processing (Single-blt logic) capabtilties
64K Program Memory address space
64K Data Memory address space
4K bytes of on-chip Program Memory
128 bytesof on-chip Data RAM
32 bidirectional and individually addressable 1/0 lines
Two 16-bit timer/counters
Full duplex UART
6-source/5-vector interrupt structure with two priority levels
On-chip clock oscillator
The basic architectural structure of this 8051 core is shown in Figure L
EXTERNAL
INTERRUPTS
,,
I
I
w II
H
BUS
CONTROL
4 1/0 PORTS
11
Po P2 PI P3
H
Q
SERIAL
PORT
TXO RXD
COUNTER
INPUTS
AODRESS/DATA
270251-1
Figure 1. Block Diagram of the 8051 Core
1-3
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