8XC51FX HARDWARE DESCRIPTION
Whenevera 16-bitaddressis used, the high byte of the
address comes out on Port 2, where it is held for the
duration of the read or write cycle. The Port 2 drivers
use the strong pullups during the entire time that they
are emitting addressbits that are 1s. This occurs
when
the MOVX @ DPTR instruction is executed. During
this time the Port 2 latch (the Special Function Regis-
ter) does not have to contain 1s, and the contents of the
Port 2 SFR are not moditied. If the external memory
cycle is not immediately followed by another external
memory cycle the undisturbed contents of the Port 2
SFR will reappearin the next cycle.
If an 8-bit address is being used (MOVX @ Ri), the
contents of the Port 2 SFR remain at the Port 2 pins
throughout the external memory cycle. In this casG
Port 2 pins can be used to page the externaldata mem-
ory.
In either case, the low byte of the addressis time-multip-
lexed with the data byte on Port O.The ADDRESS/
DATA signal drives both FETs in the Port Ooutput
buffers. Thus, in externalbus mode the Port Opins are
not open-drain outputs and do not require external
pullups. The ALE (Address Latch Enable) signrd
should b-eused to capturethe addressbyte into an ex-
ternal latch. The address byte is valid at the negative
transition of ALE. Then, in a write cycle, the data byte
to be written appearson Port Ojust before~ is acti-
vated, and mrnains
there until after ~ is deactivated.
In a read cycl%the inmrningb-yte iaaccepted at PortO
just before the read strobe (RD) is deactivated.
During Sny
access to externalmemory, the CPU writes
OFFH to the Port Olatch (the Special Function Regis-
ter), thus obliterating the information in the Port O
SFR. Also, a MOV POinstruction must not take place
during external memory accesses.
If the user writes to
Port Oduring an external memory fetch the incoming
code byte is corrupted.Therefore,do not write to Port
Oif external programmemory is used.
External Program Memory is accessed
under two con-
ditions:
1. Wheneversignal ~ is active, or
2. Wheneverthe programcounter (PC) contains an ad-
dressgreaterthan IFFFH (8K) for the 8XC51FA or
3FFFH (16K) for the 8XC51FB,
or 7FFFH (32K)
forthe87C51FC.
This requiresthat the ROMless veraionshave~ wired
to Vss enable the lower 8K, 16K, or 32K program
bytes to be fetched from external memory.
When the CPU is executing out of external Program
Memory, all 8 bits of Port 2 are dedicated to an output
function and may not be used for generalpurpose I/O.
During external programfetches they output the high
byte of the PC with the Port 2 driversusing the strong
puUupsto emit bits that are 1s.
5.0 TIMERS/COUNTERS
The
C51FXhasthreeid-bitTimer/Counters:TimerO,
Timer 1, and Tinter 2. Each consists of two 8-bit regis-
ters, THx and TLL (X = O,1, and 2). All three can be
configuredto operateeitheras timersor event counters.
In the Timer function, the TLx registeris incremented
every machine cycle. Thus one can think of it as count-
ing machine cycles. Since a machine cycle consists of 12
oscillator periods, the count rateis 1/12 of the oscilla-
tor frequency.
In the Counter function, the registeris incremented in
response to a l-to-O transition at its correspondingex-
ternal input pin-TO, Tl, or T2. In this function, the
externalinput is sampledduringS5P2 of everymachine
cycle. When the samplesshow a high in one cycle and a
low in the next cycle the count is incremented. The
new count value appearsin the registerduring S3P1 of
the cycle following the one in which the transition was
detected. Since it takes 2 machine cycles (24 oscillator
periods) to remgnixe a l-to-O transition,the maximum
count rate is 1/2,of the oscillator frequency. There are
no restrictions on the duty cycle of the exte.malinput
signal, but to ensure that a given level is sampled at
least once before it chang~ it should be held for at
least one full machine cycle.
In addition to the Timer or Countersektion, Timer O
and Timer 1 have four operatingmodes from which to
select: Modes O-3. Timer 2 has three modes of opera-
tion: Capture,Auto-Reload, and Baud Rate Generator.
5.1 Timer Oand Timer 1
The Timer or Counter fimction is selected by control
bits Cfi in the Special Function Register TMOD (Ta-
ble 5). These two Timer/Counters have four operating
mod= which are selected by bit-pairs (Ml, MO) in
TMOD. Modes O,1, and 2 are the same for both Tim-
er/Counters. Mode 3 operationis differentfor the two
timers.
MODE 0
Either Timer Oor Timer 1in
Mode O is an 8-bit Cmm.
ter with
a divide-by-32 prescaler. Figure 8 shows the
Mcde Ooperationfor either timer.
In this mode, the Timer register is contlgured as a
13-bitregister.As the count rolls overfrom all 1sto all
0s, it sets the Timer interrupt flag TFx. The counted
input is enabledto the Timer when TRx = 1and either
GATE = Oor ~ = 1. (Setting GATE = 1 allows
the Timer to be controlled by external input INTx, to
facilitate pulse width measurements).TW and TFx are
5-12
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