Intel MCS 51

M=@-51 PROGRAMMER’SGUIDEAND INSTRUCTION SET
ASSIGNING HIGHER PRIORITY TO ONE OR MORE INTERRUPTS:
In order to assignhigher priorityto an interrupt the correspondingbit in the 1Pregistermust be set to 1.
Rememberthat whilean interruptservieeis in progress,it cannotbe interruptedbya loweror samelevelinterrupt.
PRIORITV WITHIN LEVEL:
Prioritywithin levelis onlyto resolvesimultaneousrequestsof the sameprioritylevel.
Fromhigh to low,interrupt sourcesare listed below:
IEO
TFo
IE1
TF1
RI or TI
TF2 or EXF2
1P:INTERRUPT PRIORITY REGISTER. BIT ADDRESSABLE.
If the bit is O,the correspondinginterrupt has a lowerpriority and if the bit is 1the correspondinginterrupt has a
higherpriority.
I
— —
PT2
Ps PTl
Pxl PTO Pxo
—
1P.7
—
1P.6
PT2 1P.5
Ps 1P.4
Pm 1P.3
Pxl 1P.2
PTo
1P.1
Pxo 1P.O
Not irnplementi reservedfor future use.*
Not implemented,reservedfor future use.*
Detinesthe Timer 2 interrupt priority level(8052only).
Definesthe SerialPort interrupt prioritylevel.
Definesthe Timer 1interrupt priority level.
DefinesExternalInterrupt 1priority lexwl.
Definesthe TimerOinterrupt prioritylevel.
Definesthe ExternalInterrupt Oprioritylevel.
*Usersoftwareshould not write 1sto reservedbits. Theaebits may be used in fiture MCS-51productsto invoke
newfeatures. In that case,the reset or inactivevalueof the newbit willbe O,and its active valuewillbe 1.
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