intd.
8XC52/54/58 HARDWARE DESCRIPTION
Table
2. 8XC5X SFRMapandResetValues
OF8H
OFOH
OE8H
OEOH
OD8H
ODOH
oC8H
OCOH
OB8H
OBOF
oA8k
OAOl-
98t
9ot
881-
8ot
L
B
)0000000
ACC
30000000
Psw
Dooooooo
T2CON
T2MOD
RCAP2L
RCAP2H TL2
TH2
OoooooooXxxxxxoo 000000000000000000000000
00000000
1P
SADEN
Xooooooo
00000000
P3
IPH
11111111
Xooooooo
IE
SADDR
OoooooooOooooooo
P2
11111111
SCON SBUF
00000000Xxxxxxxx
P1
11111111
TCON TMOD
TLO TL1 THO
TH1
0000000
0 00000000
Ooooooo0 00000000
00000000
OoOmooo
Po SP
DPL DPH
PCON
1111111
1 00000111
00000000 0000000
0
00000000
OFFH
OF7H
OEFH
OE7H
ODFH
OD7H
oCFH
OC7H
OBFH
, OB7H
OAFH
OA7H
9FH
97H
8FH
~ 87H
TimerRegist
ers-flmtrol and status bits areeontairred
Interrupt Regiate-The individual interrupt enable
in registersT2CON and T2MOD for Timer 2. The reg-
bits are in the IE register.Two prioritiescan be set for
ister pair (RCAP2H, RCAP2L) are the Capture/Re-
each of the 6 interrupt sources in the IP register. The
load registersforTimer 2 in Id-bit capturemode or 16-
IPH registerallows four priorities.
bit aut&reload mode.
Serial Port Regiaters-RegM.ers SADDR and SA-
TIMER 2
DEN are used to define the Given and the Broadcast
addresses
for the Automatic Address Recognition fea-
Timer 2 is a id-bit Timer/Counter which can operate
ture.
either as a timer or an event counter.This is selectable
by bit Cm in the SPR T2CON (Table 3). It has three
4-4
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