EasyManuals Logo

Intel MCS 51 User Manual

Intel MCS 51
334 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #328 background imageLoading...
Page #328 background image
ii@l.
83C152 HARDWARE DESCRIPTION
6.0 GLOSSARY
ADR0,1,2,3(95H, OA5H,OB5H,OC5H)- Address
Match Registers0,1,2,3- The contents of these SFRS
are comparedagainst the address bits from the serial
data onthe GSC. If the addressmatchesthe SFR,then
the C152accepts that frame. If in 8 bit addreaaing
mode,amatchwith artyofthe fourregisterswilltrigger
acceptance.In
16 bit addressing mode, a match with
ADR1:ADROor ADR3:ADR2will be accepted.Ad-
dresslengthis determinedby GMOD (AL).
AE - AlignmentError, see RSTAT.
AL -
AddressLength,see GMOD.
AMSKO,l(OD5H,OE5H)- AddressMatch Mssk0,1-
I&ntifieswhich bits in ADRO,l are “don’tcare” bits.
Settinga bit to 1 in AMSKO,l identifiesthe corre-
spondingbit in ADDRO,I as not to be
examinedwhen
comparingaddresses.
BAUD- (941-1)Containsthe programmablevaluefor
thebaudrate generatorforthe GSC.Thebaudrate will
equal(fose)/((BAUD+ 1) X 8).
BCRLO,l(OE2H,OF2H)- Byte Count Register Low
0,1- Containsthe lowerbyte of the byte count.Used
duringDMA transfers to identifyto the DMA chan-
nelswhenthe transfer is complete.
BCRHO,l(OE3H,OF3H)- Byte Count RegisterHigh
0,1- contains the upperbyte of the bytecount.
BKOFF(OC4H)- BackoffTimer- Thebaokofftimer is
an eightbitcount-downtimerwitha clockperiodequal
to one slot time. The backoff time is used in the
CSMA/CDcollisionreardutionalgorithm.
BOF - Beginningof Frame flag - A term commonly
used whendealing with paoketized&ta. Signifiesthe
beginningof a frame.
CRC- CyclicRedundancyCheck- An error checking
routinethat mathematicallymanipulatesa valuedepen-
dent on the incomingdata. The purpme is to identify
whena frame haa beenreceivedin error.
CRCE- CRCError, see RSTAT.
CSMA/CD - Stands for Carrier sen% Multiple Ac-
cess,withCollisionDetection.
CT - CRCType,see GMOD.
DARLO/1(OC2H,OD2H)- DestinationAddressReg-
ister Low0/1 - Containsthe lowerbyteof the destina-
tions’addreaswhenperformingDMA trsnsfers.
DARHO/1(OC3H,OD3H)- DestinationAddressReg-
ister Low0/1 - Containsthe upperbyteof the destina-
tions’addrcaswhen performingDMA
transfers.
DAS- DestinationAddressSpace,seeDCON.
DCJ - D.C. Jam, see MYSLOT.
DCGNO/1(092H,093H)
7654321
0
I DAS I IDA ! SAS I ISA I DM ! TM I DONE I Go I
TheDCONregisterscontrolthe operationofthe DMA
chasmelsby dete
rminingthe sourceofdata to be trans-
ferred,thedestinationofthe data to betransfer,and the
variousmodeaof operation.
DCON.O(00) - EnableaDMA Transfer - When set it
enables a DMA channel. If block mode is set then
DMA transfer starts as soon as possibleunder CPU
control. If d
emrmdmode is set then DMA transfer
starts whena demandis assertedand recognized.
DCON.1 (DONE) - DMA Transfer is Complete -
Whenset the DMA transfer is complete.It is set when
BCR equals O and is automatically reset when the
DMA vectorsto its interrupt routine. If DMA inter-
rupt is disabledand the user softwareexecutesa jump
on the DONE bit then the user software must also
reset the donebit. If DONE is not set, then the DMA
transfer is not complete.
DCON.2 (TM) - Transfer Mode - When set, DMA
burst transfersare usedif the DMA channelis config-
ured in block modeor external interrupts are used to
initiate a transfer if in Demand Mode. When TM is
clear~ Alternate CycleTransfersare used if DMA is
in the BlockMode,or LocalSerialcharmel/GSCinter-
rupts are usedto initiatea transfer ifin DemandMode.
DCON.3 (DW - DMA channel Mode - When set,
DemandModeis used and whencleared, BlockMode
is used.
DCON.4 (ISA) - Increment Source Address - When
m the sourceaddressregistersare automaticallyincre-
mentedduringeachtransfer. Whencleared,the source
addressregistersare not incremented.
DCON.5(SAS)-SourceAddressSpace- WhenW6the
sourceof data for the DMA transfers is internal data
memoryifautoincrementisalsoset. Ifautoincrernentis
not set but SASis, then the sourcefor data willbe one
ofthe SpecialFunctionRegisters.WhenSASis cleared,
the sourcefor data is externaldata memory.
DCON.6 (IDA) -
Increment Destination Address
Space- Whenset, destinationaddress registemare in-
cremented once after each byte is transferred. Where
cleared,the destinationaddress registersare not auto-
maticallyincremented.
7-64

Table of Contents

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the Intel MCS 51 and is the answer not in the manual?

Intel MCS 51 Specifications

General IconGeneral
BrandIntel
ModelMCS 51
CategoryMicrocontrollers
LanguageEnglish

Related product manuals