Intel MCS 51 User Manual

infd.
HARDWARE DESCRIPTION OFTHE 8051,8052 AND 80C51
Each of these interrupt sourcescan be itldividdy en-
abledor disabledby settingor clearin
g a bit in Special
Function Register IE (Figure 22). IE contains also a
globaldisablebit, EA, whichdisablesall interrupts at
once.
Note in Figure 22 that bit position IE.6 is unimple-
mented.In the 8051sbit positionIE.5 is also tmimple-
mented.User softwareshouldnot write 1sto these bit
positions,since they may be used in future MCS-51
products.
PriorityLevelStructure
Each
interrupt source can also be individuallypro-
grammed to one of two priority levels by setting or
clearinga bit in SpecialFunction Register 1P (Figure
23). A low-priorityinterrupt can itself be interrupted
bya high-priorityinterrup~but not byanotherlow-pri-
ority interrupt. A high-priority interrupt can’t be inter-
rupted by ~y other-int&rupt-aource.-
(MSB)
(LSB)
—
— PT2 PS PTl Pxl PTo Pxo
Riwity bit = 1 assignshighpriortty.
Priorftybit = Osssignslow priority.
Symbol Poeitforl Funefion
—
IP.7
reserved
IP.6 resewed
PT2 IP.5 Tmer2 intemuptprie+ftybit.
Ps IP.4
Swisl Portintenuptprioritybl
PTl IP.3 Timer 1 intenuptprimityMt.
Pxl IP.2 Externalintenupt1 pttofitybit
MO IP.1 lim6r0 interruptpttoiitybit.
Pxo IP.O ExtemslintenuptOprioritybit
User soffwareshouldneverwite 1$ to unimplementedbits,since
theYmbe usedifIfufurs M@51 P+oducts.
Figure 23. 1P:Interrupt Priority Register
If two requestsof dikentpriority levelsare received
simultaneously,the request
of higher priority level is
serviced.
If requestsof the same priority levelare re-
ceivedsimultaneously,an internal pollingsequencede-
termines which requestis serviced.Thus within each
priority levelthereis a secondprioritystructure deter-
minedby the pollingsequence,as follows:
Source
Priority Within Level
1.
IEO
(highest)
2.
TFO
3.
IE1
4. TF1
5.
RI +Tl
6. TF2 + EXF2
(lowest)
Note that the “prioritywithin level”structureis only
usedto
resolvem“muitaneousrequestsof thesomeprion-
ty level.
The
1P register containsa numbesof unimplemented
bits. IP.7 and IP.6 are vacant in the 8052s,and in the
8051sthese and IP.5 are vacant. User softwareshould
not write 1sto these bit positions,since they may be
usedin future MCS-51products.
How InterruptsAre HandIed
The interrupt flagsare sampledat S5P2of everyma-
chine cycle.The samplesare polledduringthe follow-
ing machinecycle.The 8052’sTimer 2 interrupt cycle
is ditkrent as describedin the ResponseTimeSection.
Hone of the ilagswasin a set conditionat S5P2ofthe
P~
“ g cycle the pollingcycle will find it and the
interrupt systemwillgeneratean L-CALLto the appro-
priate serviceroutine,providedthis hardwere-generat-
ed LCALLis notblockedbyany of the followingcon-
ditions:
1. An interrupt of equal or higherpriority levelis al-
ready in progress.
2. The current (polling)cycle is not the final cycle in
the executionofthe instructionin progress.
3. The instructionin progressis RETI or any writeto
the IE or 1Pregisters.
Anyof thesethreeconditionswillblockthe generation
of the LCALLto the interrupt serviceroutine. tXmdi-
tion 2 cn3urcethat the instruction in progresswilt be
ISEP21 % I
m ‘:
A
A
.... .
INTERRU~ LONGCALLTO INIERRUPTHOUllNE
AREPOLLSO IM’ERRUPT
INTERRUPT INTERRUPT
GOES
LATCHEO
VECTORAOOQESS
ACTWE
270252-20
Ttisisthefeetestpossible reeponee vhn C2isthefinel cydeofaninettuctien ottwrthert RETI oranaeaesto IEorlP.
Ftgure24. Interrupt ResponseTimingDisgrem
3-24

Intel MCS 51 Specifications

General

Brand	Intel
Model	MCS 51
Category	Microcontrollers
Language	English