int#
87C51GB HARDWARE DESCRIPTION
14.1 IdleMode
An instructionthat sets the IDL bit csuaesthat to be
the last instructionexecutedbeforegoinginto the Idle
mode. In the Idle mode, the internal clock signal is
gated offto the CPU, but not to the IntermpL Timer,
and SerialPort functions.The PCA and PCA1timers
ed eitherto pauseor continueoperat-
Canbeprogramm
ingduringIdle withthe CIDL (CIIDL) bit in CMOD
(CIMOD). TheCPU ststus is preservedin its entirety:
the Stack Pointer, Program Counter, Program Status
Word, Accumulator,and all other registers rttaintsin
their data during Idle. The port pins hold the logical
statestheyhadat the time Idle wasactivated.ALE and
PSENholdat logichighlevels.Refer to Table27.
Table27.Statusof theExternalPins
duringidieMode
Ports
Pwrsm
ALE
~
porto
Port1
Port2
345
Memory
,,
Internal 1 1 Date Data Data Data
Extemai 1 1
Fiost Data Address Data
Therearetwowaysto
terminatethe IdleMode.Activa-
tion of any enabledinterrupt will causethe IDL bit to
beC]=ed byhardware
terminatingthe Idlemode.The
interrupt willbe serviced,and foUowingRETI the next
instructionto beexecutedwillbe the onefollowingthe
instructionthat put the deviceinto Idle.
The flagbits (GFUand GF1 in PCON)canbe used to
giveso indicationif an interrupt occurredduringnor-
mal operationor duringIdle. For example,an ittstruc-
tionthat activatesIdle can alsoset oneorbothflagbits.
WhenIdle is termina
ted by an interrupt, the interrupt
serviceroutinecan examin
e the flagbits.
The otherwayof terminatingthe Idle modeis with a
hardware reset. Sincethe clock oscillator is still run-
ning,the hardwareresetneedsto beheldactivefor only
two machinecycles(24 oscillatorperiods)to complete
the reaet.
Thesignalat the RESETpin clearsthe IDL bit directly
and asynchronously.At this time the CPU resumes
programexecutionfromwhereit left off;that ~ at the
instruction followingthe
one that invokedthe Idle
Mode.AsshownintheResetTimingdiagram,twoor
threemachinecyclesof programexecutionmaytake
placebeforetheinternalreactalgorithmtakes
control.
On-chiphardwareinhibitsaccess
to the internrdRAM
duringthis time,but
accessto theport pinsisnot inhib-
ited. To eliminatethe possibilityofunexpectedoutputs
at the port pins,the instructionfollowingthe one that
invokesIdleshouldnot be onethat writesto a port pin
or to externalData IWM.
14.2 PowerDownMode
An instructionthat setsthe PDbit causesthat to bethe
last instructionexecutedbefore goinginto the Power
Down mode. In this mode the on-chip oscillator is
stopped. With the clock frosen, all functions are
stopped,but the on-chip RAM and S- Function
Registersare held.The port pinsoutputthe valuesheld
by their respectiveSFRS,and ALE and PSENoutput
lows.In PowerDown,VW canbe reducedto as lowas
2V.Care mustbetaken,however,to ensurethat VCCis
not reducedbeforePowerDownis invoked.If the Os-
cillator Fail Detect circuitry is not disabledbeforeen-
tering powerdown,the part willmet itself(seeSection
11.0 “oscillator Fail Detect”). Table 28 shows the
status of externrdpinsduring PowerDownmode.
Tabie28.Statusof theErrtemsiPine
duringPower
Down Mode
internal O 0
Date Data Data Date
External O 0 Fioat Data Date Date
The 8XC51GBcan exit Power Down with either a
hardware reset or external interrupt. Reset redetines
most of the SFRSbut does not change the on-chip
RAM.An externalinterrupt allowsboth the SFRSand
the on-chipRAMto retain their values.
To properlyterminatePower Downthe reset or exter-
nal interrupt shouldnot be executedbeforeVCCis re-
stored to its normaloperating leveland must be held
activelongenoughfor the oscillatorto restart and sta-
bilize(normallylessthan 10ins).
With so externalinterrupt, ~0 or INTI mustbe en-
abledand con@uredas level-sensitive.Holdingthe pin
low restarts the oscillator and bringingthe pin back
high completesthe exit. After the RETI instructionis
executedin the interrupt serviceroutine, the next in-
struction willbe the one followingthe instructionthat
put the devicein PowerDown.
14.3 PowerOff Flag
ThePowerOffFlag(PW) locatedat PCON,4issetby
hardwarewhenVCCrises fromOVto 5V.POFcartdSO
be set
or clearedby software.This allowsthe user to
distinguishbetweena “cold start” reset and a “warm
start” reset.
A cold stsrt reset is one that is coincidentwith Vcc
beingturned on to the deviceafter it wasturned off.A
warmstsrt resetoccurswhileVCCisstillappliedto the
deviu and could be generated, for axamplej by a
WatchdogTimeror an exit from PowerDown.
6-51
To Next Page
Loading...
Need help?
General
