inl#
83C152 HARDWAREDESCRIPTION
GO is the enablebit for the DMA Channelitself.The
DMA Channelis inactiveif GO = O.
PCON SMOD I ARE I REQ ] GAREN I XRCLK I GFIEN I PDN I IDL
ARBenables the DMAlogicto detect~ andgener-
ate HLDA.Afterit has activatedHLDA, the C152will
notbegina newDMA to or from External Data Mem-
ory as long as ~ is seento be active. This logicis
disabledwhenARB = O,and enabledwhenARB = 1.
REQenablesthe DMAlogicto generate~ and de-
tect HLDA beforeperforminga DMA to or from Ex-
ternal Data Memory.After it has activated ~, the
C152willnotbeginthe DMA until= is seento be
active.This logicis disabledwhen REQ = O,and en-
abledwhenREQ = 1.
5.0 INTERRUPTSTRUCTURE
The 8XC152retainsall fiveinterruptaof the 80C51BH.
Sixnewinterruptsare addedin the 8XC152,to support
its GSCand the DMA features.They are as listedbe-
low,and the flagsthat generatethem are shownin Fig-
ure 5.1.
GSCRV
— GSCReceiveValid
GSCRE — GSCReceiveError
GSCTV — GSCTransmI
“tValid
GSCTE — GSCTransmitError
DMAO — DMAChanmelODone
DMA1 — DMAChannel 1 Done
As shownin Figure5.1,the ReceiveValidinterruptean
be signatedeither by the RFNE tlag (ReceiveFIFO
Not Empty), or by the RDN flag (Receive Done).
Whichone of these flagscausestie interrupt depends
on the setting of the DMA bit in the SFR named
TSTAT.
DMA = Omeans the DMA hardware k not config-
ured to servicethe GSC,so the CPU will serviceit in
softwarein responseto the Receive FIFO not being
empty-In that case,RFNE generatesthe ReceiveValid
interrupt.
DMA = 1meansthe DMA hardwareis configuredto
servicethe GSC, in whichcase the CPU need not be
interrupted till the receiveis complete. In that case,
RDN generatesthe ReceiveValidinterrupt.
Sknkrly the T
ransmitValidinterrupt ean be signaled
eitherby the TFNF flag(TransmitFIFO Not Full),or
by the TDN flag (Transmi
t Done), depending on
whetherthe DMA bit is Oor 1.
Note
thatsettingthe DMAbit doesnot itaelf~figure
the DMA channelsto seMee the GSC. That job must
be doneby softwarewritesto the DMA registers.The
DMA bit only seleots whether the GSCRV and
GSCTVinterruptsare flaggedbya FIFO needingserv-
ice or by an “operationdone”signal.
The Receive and Transmi
t Error interrupt flags are
generatedbythe logicalORofa numberoferror condi-
tions,which are describedin Section3.6.5.
Each interrupt is assigneda freedlocationin Program
Memory,and the interrupt causesthe CPU to jump to
that location. All the interrupt fiags are sampled at
S5P2of everymachineCYCIGand then the samplesare
sequentiallypolled during the next machine cycle. If
more than one interrupt of the samepriority is activq
the one that is highestin the pollingsequenceis serv-
iced first. The interrupts and their fixed locations in
ProgramMemoryare listedbelowin the order of their
pollingsequence.
270427-42
2EP--CRE
270427-44
7FNF ‘1 DMA= ~
$%+.s.
~N d MA. 1
270427-45
IaED-’”m
270427-46
OONE~OMAO
(OCONO.1)
270427-47
‘NE ~DMAl
(OCON1.1)
270427-4S
Figure 5.1. Six New Interrupts in the 8XC152
7-60
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