Intel MCS 51

intdo
HARDWARE DESCRIPTION OF THE 8051,8052 AND 80C51
STATE4 STATE 5 2TATE 6 STATE 1 STATE2 STATE3 STATE4 STATE 5
I‘11’2 IPllP2IPI1’2I‘11’2I‘11’2 I PI1’2IPllP2I‘1I‘2I
XTAIJ
“’~
~:
1
1
PCLOUTF
PROGRAM MEMORV
16exramu
PO:
DPLORRI
OuT
OATAOUT
‘2
PcHOn
oPHoRP2amour
I
PctlOn
P2em
P2eFu
270252-31
Figure38.External Data Memory WriteCycle
STATE4 STATE 6 STATE6 2TATE 1 STATE 2 STATES STAlE4 STATES
PllP21PllP21Pl lmlnlmlmlnlmlnl nlmlPllml
Irrk
“–’HpD” x:”
NovPowr,eRc:
OLOOATA
N2WOATA
s!~
+ +nxo ---
RxoeAuPLeo+ +
270252-32
Figure 39. Port Operation
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