in~e
83C152 HARDWARE DESCRIPTION
2.2 Interrupt Structure
interruptsand IPN1 (F8H) for settingthe priority.For
an explanationonhowthe priorityofinterruptsaffects
TheC152retains all fiveinterruptsofthe 80C51BH.In
their operationpleasereferto the MCS-51Architecture
additiorLsixnewinterrupts havebeenaddedfor a total
and Hardware Chapters io the Intel EmbeddedCon-
of 11availableinterrupts. TwoSFRShavebeerradded
troller Handbook.A detailed descriptionon how the
to the C152for control of the new interrupta. These
interrupts function is in the MC$W51Architectural
added SFRS are IEN1 (C8H) for enabling the
Overview.
I
IEN1 FUNCTIONS
I
Symbol
I
Position Vector Function
—
IFN1 7 I
I
RFGFBVFn sm~do note~st on chip.
I
I
.-. . . . .
I 1
------- . -- -..
——-——. .——
N1.6 i
I RESERVED
anddonotexistnn~hin
I
—
IEI -. “.. -...~.
EGSTE IEN1.5 04BH
GSC
TRANSMITERROR-Theinterruptserviceroutineat
4BHisinvokedifNOACKorTCDTisset
whenthe GSCis
I
I I
I
underCPUcontrolandEGSTEisenabled.Thisinterrupt
serviceroutineisinvokedifNOACK,TCDT,orURissetwhen
I
the GSCisunderDMAcontrolandEGSTEisenabled.
EDMA1 IEN1.4 053H DMACHANNELREQUESTl-The interruptserviceroutine
EGSTV IEN1.3
EDMAO IEN1.2
043H
03BH
at 53H isinvokedwhenDCON1.1(DONE) isset and EDMA1
isenabled.
GSCTRANSMIT VALID-lTre
interruptservice routineat 43H
isinvokedifTFNF isset whenthe GSC isunder
CPUcontrol
andEGSTVisenabled.Thisinterruptserviceroutineis
invokedif
TDN isset whenthe GSC isunderDMA controland
EGSTV isenabled.
DMA CHANNEL REQUEST (+The interruptserviceroutine
at 3BH willbe invokedwhenDCONO.1(DONE)issat and
EDMAOisenabled.
EGSRE
EGSRV
IEN1.1
IEN1.O
033H
02BH
GSC RECEIVE ERROR-The interruptserviceroutineat 33H
isinvokedifCRCE,OVR, RCABT,orAE isset whenthe GSC
isunderCPU or DMA controlandEGSRE isenabled.
GSC RECEIVE VALID-The interruptseMce routineat 2BH
isinvokedifRFNE is setwhenthe GSC is underCPU control
and EGSRVisenabled.Thisinterruptserviceroutineis
invokedif RDN issetwhentheGSC isunderDMAcontroland
EGSRV
is enabled.
IPN1 is used the same way the current 80C51BHinterrupt priority register (1P)is. By assigninga “l” to the
approptite bit,thst interrupthasa higherprioritythan an interruptwitha “O”assignedto it in the priorityregister.
The newinterrupt priority register(IPN1) contentsare:
Symbol Position
Function
PGSTE IPN1.5 GSCTRANSMIT ERROR
PDMA1 IPN1.4 DMA CHANNELREQUEST 1
,
I
PGSTV
IPN1.3 GSCTRANSMITVALID
PDMAO
IPN1.2 DMA CHANNELREQUEST O
PGSRE
IPN1.1
GSC RECEIVEERROR
PGSRV
IPN1.O
GSC RECEIVEVALID
7-11
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