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Intel MCS 51 User Manual

Intel MCS 51
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intd.
87C51GBHARDWAREDESCRIPTION
Immediatelyafter reset, the user’ssoftwarecan check
the status of the POF bit. POF = 1worddindicatea
cold start. The Aware then clears POF and corn-
mencea its tasks. POF = O immediatelyatler reset
wouldindicatea warm start.
Vcc must remain
above3Vfor POF to retain a O.
15.0 EPROM/OTPPROGRAMMING
The 8XC51GBuses the fast “Quick-Puke”Programm-
ing algorithm. The devices program at Vpp =
12.75V(andVcc = 5.OV)usinga seriesof five 100pa
PROG pukesper byte programmed.
15.1 ProgramMemoryLock
In
somemicrocontrollerapplicationsit is desirablethat
the ProgramMemorybe securefrom softwarepiracy.
The 8XC51GBhas a three-levelprogramlock feature
whichprotectsthe code of the on-chipEPROM/OTP
or ROM.
Within the EPROM/OTP/ROM are 64 bytes of En-
CIYPti~ Array that are initially unprograrnm
ed (all
1s). The user can program the Encryption*Y to
encrypttheprogrameodebyteaduringEPROM/OTP/
ROM verification.The verificationprocedure is per-
formedas usualexceptthat esoh codebyte comesout
exclusive-NOR’ed(XNOR) with one of the keybytes
Therefore,to readthe ROM codethe userhas to know
the 64 keybytesin their proper sequeru.
Unprogrammed bytes have the valueOFFH.So if the
EncryptionArray is left unprogramrn
ed, all the key
bytes have the value OFFH. Since any code byte
XNORedwithOFFHleavesthe byteunchanged,leav-
ing the EncryptionArray unprogrammedin effectby-
- the enWption feature.
PROGRAMLOCKBITS
Alsoincludedin the Program Lack schemeare three
LockBitswhichcan be programmedto disablecertain
functionsas shownin Table 29.
TOobtain
maximumsecurityof the on-boardprogram
and data,all 3Lock
BitsandtheEncyptionArray must
be
programmed.
ErasingtheEPROMalsoerasestheEncryptionArray
andtheLockBitsj
returningthepartto fullfunctionali-
ty.
Table29.EPROM/OTPLockBite
Program
LockBite
LogicEnabled
LB1 LB2 LB3
Uuu
No
ProgramLockfeatures
enabled.(CodeVerifywillstill
beencryptedbythe
EncryptionArray.)
Puu
MOVCinstructionsexecuted
fromexternalprogram
memoryaredisabledfrom
fetchingcodebytesfrom
internalmemory.EZ is
sampledandlatchedon
reset,andfurther
programmingofEPROMis
disabled.
PPU
Sameasabove,butVerifyis
alsodisabled(option
availableonEPROMonly).
PPP Sameasaboveandall
externalprogramexecutionis
inhibitedandinternalRAM
oannotbereadexternally.
All other combinations of lock bits may produce indetermi-
nate
resultsand shouldnotbe used
16.0 ONCEMODE
The ONCE (ON-CircuitEmulation)mode facilitates
testing and debuggingof systemsusingthe 8XC51GB
without havingto removethe dexieefrom the circuit.
The ONCE modeis invokedby:
1.g
ALElowwhilethe deviceis in resetand
PSENis high;
2. HoldingALE lowas RSTis deactivated.
Whilethe deviceis in ONCEmode,the Port Opins go
into a float state, and the other port pins, ALE, and
~ are weakly pulled high. The oscillator circuit
remains active. While the &vice is in this mode, an
emulatoror test CPU can be usedto drive the circuit.
Normal operationis restoredafter a valid reset is ap-
plied.
17.0 ON-CHIP OSCILLATOR
The on-chiposcillatorfor the CHMOSdevicesconsists
of a single stage linear inverter intended for use as a
6-52

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Intel MCS 51 Specifications

General IconGeneral
BrandIntel
ModelMCS 51
CategoryMicrocontrollers
LanguageEnglish

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