Intel MCS 51 User Manual

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HARDWARE DESCRIPTIONOF THE 8051,8052 AND 80C51
As data bits comein fromthe right, 1sshiftout to the
left. Whenthe start bit arrivesat the leftmostposition
in the shiftregister (whichin Modes2 and 3 is a 9-bit
register),it flags the RX Controlblockto do one last
shit%load SBUF and RIM,and set RI. The signalto
loadSBUFandRB8,andto set RI, willbegeneratedif,
andonlyif,the followingconditionsare met at the time
the finalshift pulseis generated:
1)RI= O,artd
2)EitherSM2= Oorthe received9thdatabit= I
If either of these conditionsis not met, the received
three is irretrievablylost, and RI is not set. If both
conditionsare met, the received9th data bit goesinto
RB8,and the tiret 8 &ta bits go into SBUF.One bit
time later, whether the aboveconditionswere met or
not,theunitgoesbackto lookingfora l-tQ-Otransition
at the RXD input.
Notethat the valueofthe receivedstopbit is irrelevant
to SBUF,RB8,or RI.
INTERRUPTS
The 8051provides5 interrupt sources.The 8052pro-
vides6. Theseare shownin Figure 21.
The External Interrupts ~ and INT1 carseach be
eitherlevel-activatedor transition-activate&depending
on bita~ and ITl in RegisterTCON.The tlagsthat
actuallygeneratethese interrupts are bits IEQand IE1
in TCON.Whetsen externalinterrupt is generated,the
tlag that generatedit is clearedby the hardware when
the serviceroutine is vectoredto onlyif the interrupt
.J?--#GJ,
m
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I
A?--@+=
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exn (mssOMLo
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270252-19
wastransition-activated.If the interrupt waslevel-acti-
vat@ then the externalrequestingsourceis what con-
trolsthe requestflag,rather than the on-chiphardware.
The Timer Oand Timer 1 Interrupts are generatedby
TFOand TFl, whichare set by a rolloverin their re-
spectiveTimer/Counterregkters(exceptseeTimerOin
Mode3). Whena tinter interrupt is generated,the flag
that generatedit is cleared by the on-chiphardware
whenthe serviceroutineis vectoredto.
TheSerialPort Interruptis generatedbythe logicalOR
of RI andTI. Neitherof theseflagsis clearedbyhard-
ware when the cervix routine ia vectored to. In fact,
the service routine will normally have to determine
whether it was RI or TI that generatedthe interrupt,
and the bit willhaveto be cleared in software.
In the 8052,the Timer 2 Interrupt is generatedby the
logicalOR ofTF2 and EXF2.Neither oftheseflagsis
cleared by hardware when the service routine is vec-
tored to. In fact, the serviceroutinemayhave
to deter-
mine whetherit weeTF2 or EXF2 that generatedthe
interrupL and the bit will have to be cleared in soft-
ware.
All of the bite that generateinterrupt can be
setor
cleared by software,with the same result as thoughit
had beensetor clearedbyhardware.That is, interrupts
can be generatedor pendinginterrupts can be canceled
insoftware.
(MSS)
(LSB)
m]
— I E72 I ES I ~1 I EXl I ETO] EXO
Enable S4 = 1 enaMss the infwrupt
Ensble Sit = Odieebles it
symbol
Position
Function
EA
IE.7
&eek4essIIinterrupts.If EA = 0, no
intemuptwillbeeeknowledged. If EA
= I,eeehinterrupt solneeie
indbiduskyenebled wdissbled by
settingorclearing meaaeble bit.
IE.6
resewed.
ET2 IE.5
litnw2 intenupfenable bit
ES
IE.4
Serial P&t infamuptenebletit.
El-l IE.3
ITmer 1 imenupl ensbfe bit.
Exl IE2 Extarrsalinterrupt1 ertablebt
ETo
IE.t Timw Oikttanuptenablsbit.
Exo
IE.O ExterrKaintenup
tO eneblebit
Usersotiwaraslwuld navarwrits Istourtimplamwfad bits,since
~MSYbausad infutureMCS-51 @ueta
Figure22.IE:InterruptEnableRsgister
Figurs 21. MCS@-51Intarrupt Sources
3-23

Intel MCS 51 Specifications

General

Brand	Intel
Model	MCS 51
Category	Microcontrollers
Language	English