intd.
M~@-51 ARCHITEC~RAL OVERVIEW
HIGHPRIORllY
IE REGISTER
1PREGISTER
INTERRUPT
o
b
1.
+h-O+io
1 I
I
e b
TFo
/&+.
‘POLUNG
INTERRUPT
1
SEQUENCE
o
●
-&-J.
1
I
:
0 b
7FI J&o
I
I
:
0
➤
v
RI
n
J+
I
A
\
~ LyPwPNrr
270251-17
.-
Figure 19.8051 Intermpt control system
In operatiom all the interrupt tlags are latched into the
interrupt control system during State 5 of every ma-
chine cycle. The samples are polled during the follow-
ing machine cycle-If the flag for an enabled interrupt is
found to be set (l), the interrupt system generates an
LCALL to the appropriate location in Program Memo-
ry, unless some other condition blocks the interrupt.
Several conditions can block an interrupt, among them
that an interrupt of equal or higher priority level is
already in progress.
The hardware-generated LCALL csusea the contents of
the Program Counter to be pushed onto the stack, and
reloads the PC with the beginning address of the service
routine. As previously noted (Rgare 3), the service rou-
tine for each interrupt begins at a fixed location.
Only the Program Counter is automatically pushed
onto the stack, not the PSW or any other register. Hav-
ing only the PC be automatically saved allows the pro-
grammer to decide how much time to spend saving
which other registers. This enhances the interrupt re-
sponse time, albdt at the expense of increasing the pro-
-er’s bu~en of responsibility. As a result, many
snterrupt functions that are typical in control applics-
tions-togghmg a port pim for example, or reloading a
timer, or unloading a serial but%r-can otten be mm-
pleted in lms
time than it takes other architectures to
commence them.
SIMULATING A THIRD PRIORITV LEVEL IN
SOFIWARE
Some applications
require more than the two priority
levels that are provided by on-chip hardware in
MCS-51 devices. In these cases, relatively simple soft-
ware can be written to produce the same effect as a
thkd priority level.
Firat, interrupts that are to have higher priority than 1
are ssaigned to priority 1 in the 1P (Interrupt Priority)
register. The service routines for priority 1 interrupts
that are supposed to be interruptible by “priority 2“
interrupts are written to include the following code
PUSH IE
MOV
IE, #MASK
CALL
LABEL
●******
(execute service routine)
●******
POP IE
RET
LABEL RETI
1-21
To Next Page
Loading...
Need help?
General
