Intel MCS 51 User Manual

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McS@-51PROGRAMMER’SGUIDE AND INSTRUCTION SET
INTERRUPTS:
In orderto use any of the interruptsin the MCS-51,the followingthree steps must be taken.
1. 3et the EA (enableall) bit in the IE register to 1.
2. Set the correspondingindividualinterrupt enablebit in the IE registerto 1.
3. Beginthe
interruptserviceroutineat the em-respondingVectorAddressof that interrupt. SeeTablebelow.
I
Interrupt
I
Vector
Souroe
Address
I
IEO
TFO
IE1
TF1
RI &Tl
TF2 & EXF2
OO03H
OOOBH
O013H
OOIBH
O023H
O02BH
In addition,for extemafinterrupts,pins~ and INT1 (P3.2andP3.3)mustbe set to 1,anddependingonwhether
the intermpt is to be levelor transitionactivated,bits ITOor IT1 in the TCON register mayneedto be set to 1.
ITx = Olevelactivated
ITx= 1transitionactivated
IE: INTERRUPT ENABLE REGISTER. BIT ADDRESSABLE.
If the bit is O,the correspondinginterrupt is disabled.If the bit is 1,the correspondinginterruptis enabled.
EA — ET2 ES ETl EX1 ETo
EXO
EA
IE.7 Disablesallinterrupts.IfEA = O,no interrupt willbeacknowledged.IfEA = 1,eachinterrupt
sourceis individuallyenabledor disabledby settingor elearin
g its enablebit.
—
IE.6 Not implemented,reservedfor future use.*
ET2 IE.5 Enableor disablethe Timer 2 overflowor capture interrupt (8052only).
Es
IE.4 Enableor disablethe serial port interrupt.
ET1
IE.3 Enableor disablethe Timer 1overtlowinterrupt.
EX1
IE.2 Enable or disableExternalInterrupt 1.
ETO
IE.1
Enableor disablethe Timer Ooverflowinterrupt.
EXO
IE.O Enableor disableExternal Interrupt O.
*Usersoftwareshouldnot write 1sto reserv
ed bits. Thesebits maybe usedin futore MCS-51preductsto invoke
newfeatures.In that case, the reset or inactivevalueof the newbit wiltbe O,and its activevaluewillbe 1.
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Intel MCS 51 Specifications

General

Brand	Intel
Model	MCS 51
Category	Microcontrollers
Language	English