Intel MCS 51

i~.
HARDWARE DESCRIPTlONOF THE 8051,8052 AND 80C51
RECEIVE
I
WRITE
S~tF
PHASE 2 CLOCK
(%fosc)
S0S1INTERNAL BUS
TSS
MOOE 2
STOP 91T
START GEN,
‘H’mDATA
TX CONTROL
TX CLOCK TI
Sm
LOAO +
IFFH
RxD
LOAD
SBUF
TXD
~LOC~
1 n
t
n
n
n R
1
n
n
n
I WRITE TO SBUF
OATA
I
sNIPr
n n a n
11
n
I
o
n
TRANSMIT
TI
STOPRl~
r
ICLOCK 1
1
lSRESET
n
8 n
1
n
o
Rxo
n m
1
B17DETEcToR15’m’~/
m
I D1 1
02
I
D3
I
M
r
06 I
m 1
07
1
ma
SAMPLETIMES
m !4!4
m
W
Im
k.4.pP
m
Es
u
SHIT
1
n
n n
n
n
n
n
m
n
M
n
270252-17
Figure 19. Serial Port Mode 2
3-21