83C152 HARDWARE DESCRIPTION
RFIFO (OF4H)- ReceiveFIFO - RFIFO is a 3 byte
bfier that is loadedeach time the GSCreceiverhas a
byteofdata. Aaaociated withRFIFOisa pointerthat is
automaticallyupdated with each read of the FIFO. A
read ofRFIFO fetches the oldestdata in the FIFO.
RSTAT(OE81-1)- ReceiveStatusRegister
7654321 0
OR RCABTIAE
CRCE RDN
RFNE GREN HABEN
Figure 3.16. RSTAT
RSTAT.O(HABEN) - Hardware BaaedAcknowledge
Enable- If set, enables the hardwarebaaed acknowl-
edgefeature.Theuser softwareis responsiblefor setting
or clearingthis flag.
RSTAT.1(GREN) - ReceiverEnable- Whenset, the
receiverisenabledto acceptincomingframes.The user
must clear RFIFO with softwarebeforeenabling the
receiver.RFIFO is cleared by readingthe contents of
RFIFOuntil RFNE = O.Aftereachread ofRFIFO, it
takes onemachine cyclefor the status of RFNE to be
uxti setting GREN also chars RDN, CRC~ AE,
and RCABT.GREN is clearedbyhardwareat the end
ofa receptionor if any receiveerrorsare detected.The
usersoftwweis responsiblefor settingthis flagand the
GSCor usersoftwarecan clearit. Thestatus of GREN
hasno effectonwhdm the receiverdetectsa collision
in CSMA/CD mode as the receiver
input circuitry al-
ways monitom
the receivepin.
RSTAT.2(RFNE) - ReceiveFIFO Not Empty-If set,
indicatesthat the receiveFIFO containsdata. The re-
ceiveFIFO is a three bytebufferintowhichthe receive
data is loaded.A CPU read of the FIFO retrievesthe
oldeatdata and automaticallyupdatesthe FIFO point-
ers.setting GREN to a onewillclearthe receiveFIFO.
The status of this tlag is controlledby the GSC. It is
clearedif user emptiesreceiveFIFO.
RSTAT.3(RDN) - ReceiveDone-If set, indicatesthe
successfulcompletionof a receiveroperation.Will not
be set if a CRC, alignment, abort, or FIFO overrun
error occurred.The status of this tlag is controlledby
the GSC.
RSTAT.4(CRCE)- CRCError -If set,indicatesthat a
properlyaIignedframewasreceivedwitha mismatched
CRC.The status of this fig is controlled
by the GSC.
RSTAT.5 (AE) - Alignment Error - In CSMA/C!D
mode,AE is set if the receivershiftregister(an internal
serial-to-parallelconverter) is not fulland the CRC is
bad whenan EOF is detected.In CSMA/CDthe EOF
is a line idle condition(see LNI) for two bit times. If
the CRC is correct whilein CSMA/CDmode, AE is
not set and anymis-aligmnentis assumedto be caused
by dribble bits as the line went idle. In SDLC mode,
AE is set if a non-byte-alignedflagis received.CRCE
mayalsobe set. The settingof this tlagis controlledby
the GSC.
RSTAT.6(RCABT)- ReceiverCollision/Abat Detect
- If se~indicatesthat a collisionwas
detectedafterdata
hadbeen
loadedinto the receiveFIFO in CSMA/CD
mode.In SDLCmod%RCABTindicatesthat 7consec-
utiveonesweredetectedprior to the end tlag but after
data has been loadedinto the receiveFIFO. AE may
alsobe set. The settingof this flag is controlledby the
GSC.
RSTAT.7(OVR)- Overrun - If setj indicatesthat the
receiveFIFO wastill and new shift register data was
writteninto it. AE and/or CRCE mayalsobe set. The
setting of this tlag is controlledby the GSC and it is
clearedby user software.
SLOTTM(OBH)- SlotTime- Deterrnineathe lengthof
the slot time usedin CSMA/CD. A slot time equals
(SLOTTM)X (1/baud rate). A readofSLOTTMwill
givethe valueof the slot time timer but the valuemay
beinvrdidas the timeris clockedasynchronouslyto the
CPU. Loading SLOTTM with O results in 256 bit
times.
TCDCNT(OD4H)- TransmitCollisionDetect Count-
Containsthe numberofcollisionsthat haveoccurred if
probabilisticCSMA/CD is used. The user software
mustclear this registerbeforetransrm
“ttinga newframe
so that the GSCbackoffhardware can accuratelydia-
tinguiaha newframefrom a retransmit attempt.
In de
terminktic backoffmode, TCDCNT is used to
holdthe
maximumnumberof slots.
TFIFO (85H)- GSC Transmit FIFO - TFIFO is a 3
bytebufferwithan
associatedpointerthat is automati-
callyupdatedforeachwritebyusersoftware.Writinga
byte to TFIFO loads the data into the next available
locationin the transmit FIFO. SettingTEN clearsthe
transmit FIFO so the transmit FIFO should not be
written to prior to setting TEN. If TEN is alreadyset
tranamkaionbeginsas soon as data is written to TFI-
FO.
TSTAT(OD8)-TransmitStatusRegister
7
6543210
I m INOACKIURITCDTI TDNITFNFITEN IDMAI
Figure 3.17. TSTAT
TSTAT.O(DMA)- DMA Select- If set, indicatesthat
DMAchannelsare usedto servicethe GSCFIFO’sand
GSCinterruptsoccuron TDN and RDN, andalsoen-
ablesUR to becomeset. If cleared, indicateathat the
GSC is operatingin its normal mode and interrupts
occuron TFNF and RFNE. For more informationon
DMA servicingplease refer to the DMA section on
DMAaerialdemandmode(4.2.2.3).The usersoftware
is responsiblefor settingor clearingthis flag.
{46
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