i~e
83C152 HARDWARE DESCRIPTION
GMOD.7~CLK) - ExternalT
ransmitClock- If set
an external 1X clock is used for the transmitter. If
cleared the internal baud rate generator providesthe
transmit clock. The input clock is applied to P1.3
~~).
The user software is responsible for setting or
clearingthis flag. External receiveclockis enabledby
settingPCON.3.
IFS (OA4H)- Interframe Spacing- Determm
“ es the
number of bit times separatingtransmitted frames in
CSMA/CDand SDLC.A bit time is equal to l/baud
rate. Onlyeveninterfkarnespaceperiodscan be used.
The numberwritten intothis registeris dividedby two
and loadedin the moatsignificantsevenbits.Complete
interfkamespaceis obtainedby counting
this seven bit
number downto zero twice. A user softwareread of
this registerwillgivea vafuewherethe sevenmost sig-
nificantbits givesthe current countvalueandthe least
significantbit showsa oneforthe first countdown and
a zerofor the secondcount.Thevaluereadmay not be
vafidas the timm is clockedin periodsnot necessarily
associatedwiththe CPU read ofIFS. Loadingthis reg-
ister withzero results in 256bit times.
MYSLOT(OF5H)- SlotAddreasRegister
76543210
DcJ
DCR SA5 SA4 SA3
SA2 SA1 SAO
I SAn = SLOTADDRESS (BITS5 – O)
Figure 3.15. MYSLOT
MYSLOT.0,1,2, 3, 4, 5- Slot Address- The six ad-
dressbits choose1of 64slotaddreases.Address63has
the highest priority and address 1 has the lowest. A
valueof zero wilfprevent a station from transmitting
duringthe collisionresolutionperiodby waitinguntil
all the possibleslot timea haveefapsed.The user soft-
ware normallyinitializeathis addressin the operating
software.
MYSLOT.6(DCR) - DeterministicCollisionResolu-
tion Algorithm- WhenaeLthe alternatecollisionreso-
lutionalgorithmis selected.Retriggeringofthe IFS on
reappearanceofthe carrier is alsodisabled.Whenusing
this feature Alternate BaekoffModemust be selected
and several other registers must be initialized. User
softwaremust initialize
TCDCNTwith the maximum
numba ofslotsthat are mostapproptite for a particu-
lar application.The PRBS register must be set to all
onea.Thisdisablesthe PRBSbyfreezingit’s
eorttentsat
OFFH. The backoff
timer is used to count down the
numberofslotsbasedonthe slottimervaluesettingthe
periodof one slot. The user softwareis responsiblefor
settingor clearingthis
flag.
MYSLOT.7(DCJ) - D-C.Jam - Whenset selectaD.C.
type~, when
cl-, selectsA.C. typejam. The user
softwareis responsiblefor settingor clearing
this flag.
PCON(087H)
7654
3 210
SMOD ARB REQ
GAREN XRCLKGFIEN
PD IDL
PCON contains bits for power control, LSC control,
DMA control,and GSC control.Thebits used for the
GSCare PCON.2,PCON.3, and PCON.4.
PCON.2(GFIEN) - GSC Flag Idle Enable - Setting
GFIEN to a 1causedidleflagsto begeneratedbetweem
transmitted frames in SDLC mode. SDLC idle tlags
consist of 01111110 tlags creating the sequence
01111110011111110
. .....011111110. A possibleside
effectofenablingGFIEN isthat themaxim
um possible
latency from writing to TFIFO until the first bit is
transmitted increased from approximately2 bit-times
to around 8 bit-times. GFIEN has no effect with
CSMA/CD.
PCON.3(XRCLK)- GSCExternalReceiveClockEn-
able- Writinga 1to XRCLK enablesan externalclock
to be appliedto pin 5 (Port 1.4).Theexternalclockis
usedto determinewhenbits are loadedinto the receiv-
er.
PCON.4(GAREN) - GSCAuxilimyRemiverEnable
Bit- Thisbit needsto be set to a 1to enablethe recep-
tion of back-to-back SDLC frames. A back-to-back
SDLCframe is when the EOF and BOFis shared te-
tweentwo sequentialframesintendedfor the samesta-
tion on the link. If GAREN containsa Othen the re-
ceiverwillbe disabledupon receptionof the EOF and
by the time user software re-enablesthe receiver the
firstbit(s)mayhavealreadypassed,in the caseofback-
to-backframes Setting GAREN to a 1, prevents the
receiverfrom being disabledby the EOF but GREN
wilfbe cleared and can be checkedby user softwareto
determinethat an EOF has beur received.GAREN has
no effectif the GSCis in CSMA/CDmode.
PRBS (OE41-1)- Paeudo-RandomBinary Sequence-
This register contains a pseudo-randomnumber to be
usedinthe C3MA/CD backoffalgorithm.The number
is generatedby using a feedbackshift register clocked
bythe CPU phaseclocks.Writingatl onesto the PRBS
willfreezethe valueat all ones.Writinganyother value
to it willrestart the PRBSgenerator.The PRBSis ini-
tializedto all zero’sduringRESET.A read of location
OE4Hwill not necesard
“y give the seed used in the
baekoff algorithm because the PRBS counters are
clockedby internal CPU phaseclocks.This meansthe
eontentsof the PRBS may have beenaltered between
the time when the seed was generatedand before a
~READ has been internally executed.
7-45
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