Intel MCS 51 User Manual

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MCS@-51 ARCHITECTURAL OVERVIEW
states and phases for various kinds of instructions. Nor-
malIy two program fetches sre generated during each
machine cycle, even if the instruction being executed
doesn’t require it. If the instruction being executed
doesn’t need more code bytes, the CPU simply ignores
the extra fetch, and the Program Counter is not incre-
mented.
Execution of a one-cycle instruction (Figure 15A and
B) begins during State 1of the machine cycle when the
opcode is latched into the Instruction Register. A sec-
ond fetch occurs during S4 of the same machine cycle,
Execution is complete at the end of State 6 of this ms-
chine cycle.
The MOVX instructions take two machine cycles to
execute. No program fetch is generated during the see
ond cycle of a MOVX instruction. This is the ordy time
program fetches are skipped. The fetch/execute se-
quence for MOVX instructions is shown in Figure
15(D).
The fetch/execute sequences are the same whether the
Program Memory is internal or external to the chip.
Execution times do not depend on whether the Pro-
gram Memory is internal or external.
Figure 16shows the signals and timing involved in pro-
gram fetches when the Program Memory is external. If
Program Memo~xternsl, then the Program Memo-
ry read strobe PSEN is normally activated twice per
machine cycle, as shown in Figure 16(A).
If an access to external Data Memory occurs, as shown
in Figure 16(B), two PSENS are skippe$ because the
address and data bus are being used for the Data Mem-
ory access.
Note that a Data Memory bus cycle takes twice as
much time as a Program Memory bus cycle. Figure 16
shows the relative timing of the addresses being emitted
at Ports Oand 2, and of ALE and PSEN. ALE is used
to latch the low address bvte from POinto the address
latch.
r
ONE MACHINE CVCLS
T
ONE MACIUNE CYCLE
1
sl[a21s21s41aslss SIIS21S21S41SE 126
ALE
I
I
I
1
!
,
-N ~
I
I
I
1
1
I
L
r
I
1 I
1
1
I I
I
ro
1
I
I
I
1
1
WITH%)UT A
1
I
I
I
1
1
1
I
I
I
MOVX.
P2
PCH OUTX
PCH OUT
x
[
PCH OUT
x’
I
PCNOUT
1
I
I
1
t~::$m
t5i:F
ty;LL&T &T
G:v:m’lxm:m
)
I I
,
-N ~
I
1 1
I
1
I
1 I
1
E
I
1
I
I
(B)
I
I
I
I
I
WITH A
I
I
I
1
MOVX.
P2PcHc@(
! PCHOUT
x!
OPH OUT OR P2 OUT
x:
PCH OUT )( PWOUT
t P&m&T iAC:O&UT
2702!31 -16
Figure 16. Bus Cycles in MCS@-51 Oevices Extilng irom External Program Memory
1-19

Intel MCS 51 Specifications

General

Architecture	8-bit
Number of Instructions	111
Clock Speed	12 MHz
Register Size	8-bit
Internal RAM	128 bytes
Internal ROM	4 KB
External Memory	64 KB
I/O Pins	32
Timers	2
Serial Port	1
Interrupts	5
Operating Voltage	5V
UART	Yes
Program Memory	4 KB
RAM	128 bytes
Instruction Set	CISC

Summary

MCS® 51 Family of Microcontrollers Architectural Overview

THE MCS®-51 INSTRUCTION SET

Provides an overview of the MCS®-51 instruction set, optimized for 8-bit control applications.

Interrupt Structure

Overview of the 8051 interrupt structure, sources, and vectoring.

MCS® 51 Programmer’s Guide and Instruction Set

MCS®-51 INSTRUCTION SET

Provides a summary of the 8051 instruction set, including mnemonics and operands.

8051, 8052 and 80C51 Hardware Description

TIMER/COUNTERS

Describes Timer 0 and Timer 1, including operating modes and control registers.

8XC52/54/58 Hardware Description

8XC51FX Hardware Description

PORT STRUCTURES AND OPERATION

Details port structures, I/O configurations, and external memory access.

SERIAL INTERFACE

Covers serial port modes, framing error detection, and baud rate generation.

87C51GB Hardware Description

SPECIAL FUNCTION REGISTERS

Provides a map of the SFR space and their reset values.

I/O PORTS

TIMERS/COUNTERS

PROGRAMMABLE COUNTER ARRAY

SERIAL PORT

Details the serial port's modes, framing error detection, and baud rates.

INTERRUPTS

Covers interrupt sources, enable registers, and priority levels.

RESET

83C152 HARDWARE DESCRIPTION

GLOBAL SERIAL CHANNEL

DMA OPERATION

INTERRUPT STRUCTURE