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Intel MCS 51 User Manual

Intel MCS 51
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i@
87C51GB HARDWARE DESCRIPTION
Table22.Interrupt
Enable Registers
IEA
Symbol
EA
EC
ET2
ES
ETl
EX1
ETo
EXO
EAD
EX6
EX5
EX4
EX3
EX2
EC1
ESEP
Address= OA8H
ResetValue= 000000006
BitAddressable
EA
EC I ET2 ] ES ETl Exl Ho EXO
Bit 7 6 5 4 3 2 I o
Address= OA7H
ResetValue= 0000OOOOB
NotBitAddressable
EAD EX6I EX5 EX4 EX3 EX2 EC1IESEP
Bit 7 6 5 4 3 2 1 0
Enablebit= 1 enablestheinterrupt
Enablebit= Odisablestheinterrupt
Function
Globaldisablebit.IfEA=O,allInterruptsaredisabled.IfEA=1,eachInterruptcanbe
individuallyenabledordisabledbysettingorclearingitsenablebit.
PCA
interrupt enable bit.
Timer 2 interrupt enable bit
Serial Port interrupt enable bit.
Timer 1 interrupt enable bit.
External interrupt 1 enable bit.
Timer O interrupt
enablebit.
ExternalinterruptOenablebit.
A/D converterinterruptenablebit.
Externalinterrupt6enablebit.
Externalinterrupt5enablebit.
Externalinterrupt4enablebit.
Externalinterrupt3enablebit.
Externalintemspt2enablebit.
PCA1interruptenablebit.
SerialExpansionPortinterruptenablebit.
12.6 InterruptPriorities
Eachinterruptsourceon the 8XC51GBesn be individ-
uallyprogramm
ed to oneoffour prioritylevels,by set-
ting or c1
earing the bits in the Interrupt Priority (IP
and IPA) registers and the Interrupt
PriorityHigh
(IPHend
IPAH) registers.SeeTable23.The IPH reg-
istershavethesamebitmapasthe IP registerswith an
“H” addedto eachbit’sname.Thisgiveseachinterrupt
sourcetwobits for setting the prioritylevels.The LSB
of the Priority Seleet Bits is in the 1P S~ and the
MSBis in the IPH SFR.
A low-priorityinterrupt oan itself be interrupted by a
highermioritv interruut. but not by another interrtmt
of~he&ne priority.fie”highest pti&ityinterrupt*-
not be interruptedby any other interrupt source.
If twoor morerequestsofdifferentprioritylevelsare
receivedsimultaneously,
the requestof higher priority
level
is seMced.Ifrequestsofthessmeprioritylevel
are
receivedsimultaneously,an internalpolling se-
quence determines which request is serviced. Thus
within each priority lewelthere is a second priority
structure deterrmn ed by the pollingsequeneeshownin
Table24.
6-45

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Intel MCS 51 Specifications

General IconGeneral
BrandIntel
ModelMCS 51
CategoryMicrocontrollers
LanguageEnglish

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