Intel MCS 51 - Page 283

i~o
83C152 HARDWARE DESCRIPTION
Tabk 3.1 (Continued)
----- -. .
,__......—_-,
AVAILABLE~
PRE-
OPTIONS
AMBLE
JAM CLOCK
CONTROL
3 6 D c E I c D R R c s
c R x
: :
M
D
N= NOTAVAILABLE
c T
: E A 4 4 :
M= MANDATORY
1
I [ E
O= OPTIONAL
R T A k
T T
: R
P= NORMALLYPREFERRED
E
X= N/A
: &
: : E N D
L L
I
v
i
SELECTED E
1 FUNCTION :
DATAENCODING:
MANCHESTER
o 0 0 0 N M o 0 0 0 M N
NRZI o 0 N N N M o 0 0 0 N M
NRZ o 0 0 0 M N o 0 0 0 0 0
FIAGS:O1ll 1110
0 0 N N o 0 0 0 0 1 1 P
11/lDLE o 0 0 0 0 0 0 0 0 1
P 1
CRC:NONE
1 1 N N 1 1 1 1 1 1 1 1
l&BIT CCllT o 0 0 0 0 0 0 0 1 1 0 0
32-BITAUTODINII
o 0 0 0 0 0 0 0 1 1 0 0
DUPLEX:HALF
o 0 0 0 0 0 0 0 0 0 0 0
FULL o 0 N N o 0 0 0 N N N P
ACKNOWLEDGEMENT:NONE o 0 0 0 0 0 0 0 0 0 0 0
HARDWARE o 0 0 0 N o 0 0 N N o N
USERDEFINED
o 0 0 0 0 0 0 0 0 0 0
1
ADDRESSRECOGNITION:
NONE o 0 0 0 0 0 0 0 0 0 0 0
&BIT o 0 0 0 0 0 0 0 1
1
0 0
l&BIT o 0 0 0 0 0 0 0 1 1 0 0
COLLISIONRESOLUTION:
NORMAL o 0 0 0 N o 0 0 0 N M N
ALTERNATE o 0 0 0 N o 0 0 0 N M N
DETERMINISTIC o 0 0 0 N o 0 0 0 N M N
PREAMBLE:NONE
N N N N o 0 0 0 0 0 N P
8-BIT
N N o 0 0 0 0 0 1 1
0 0
32-BIT x N o 0 0 0 0 0
1 1
0 0
34-BIT
N
x o 0 0 0 0 0 1 1 0
0
JAM:D.C. o 0 x N N o 0 0 0 N M N
m o 0 N x N o 0 0 0 N M N
CLOCKING:QCrERNAL o 0 N N x
N
o 0 0 0 N o
INTERNAL o 0 0 0 N
x
o 0 0 0 0 0
CONTROISCPU o 0 0 0 0 0 x N o 0 0 0
DMA o 0 0 0 0 0 N x o 0 0 0
RAWRECEIVE:
1
1 0 0 1
1
1
1
x N 1
1
RAWTRANSMIT:
1
1
N N
1
1 1 1 N x 1 1
CSMAICD: o 0 0 0 N o 0 0 0 0 x N
SDLC: o 0 N N o 0 0 0 0 0 N x
7-19