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Intel MCS 51 User Manual

Intel MCS 51
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i~.
83C152 HARDWARE DESCRIPTION
DMA channels the sourceor destinationof the data
intended for serial transmissioncan be internal data
memory,externaldata memory,or any of the SFRS.
Theonlytasksrequiredafter initializationofthe DMA
and GSC registers are enablingthe proper interrupts
andinformingthe DMAcontrollerwhento start. After
theDMA channelsarestarted affthat is requiredofthe
CPUis to respondto error conditionsor waituntil the
endof transmission.
Initializationof the DMA channelsrequiressettingup
the control, source,and destinationaddress registers.
On the DMA channelservicingthe receiver,the con-
trolregisterneedsto beloadedasfolfows:DCONn.2=
O,this setsthe transfermodesothat responseis to GSC
interruptsand put the DMA control in alternatecycle
modq DCONn.3 = 1,this enablesthe demandmode;
DCONn.4 = O,this clears the automatic increment
optionfor the sourceaddres$ and DCONn.5 = 1,this
detbes the sourceas SFR.The DMAchannelservicing
the receiver also needs its source address register to
contain the addreas of RFIFO (SARHN = XXII,
SARLN= OF4H).Onthe DMA channelservicingthe
transmitter, the controlregister needs to be loadedas
follows:DCONn.2= O;DCONn.3 = 1;DCONn.6=
O,this clears the automatic increment optionfor the
destinationaddress;and DCONn.7 = 1, this sets the
destination as SFR. The DMA channel serving the
transmitter also requireathat its destination address
register containsthe address of TFIFO (DARHN =
XXI-I, DARLN = 85H). Assuming that DCONO
wouldbe servingthe receiverand DCON1 the trans-
mitter, DCONOwould be loaded with XX101OXOB
and DCON1wouldbe loadedwith 10XX1OXOB.The
contentsof SARHOand DARH1 do not haveany im-
pactwhenusinginternalSFRSas the sourceor destina-
tion.
Whenusingthe DMAchannelsto seMce the GSC,the
byte countregisterswillalsoneedto be initialized.
The Done flag for the DMA channel servicingthe re-
ceivershouldbe used if fixedpacket lengthsonlyare
beingtransmittedor to insurethat memoryis notover-
written by long receiveddata packets. Ovenvritingof
data can occur whenusing a smaller buffer than the
packet size. In these cases the servicingof the DMA
and/or GSCwouldbe in responseto the DMA Done
flagwhenthe bytecountreacheszero.
In somecasesthe bufk size is not the limitingfactor
and the packetlengthswillbe unknown.In thesecases
it would be desirableto eliminatethe functionof the
Donetlag. To effectivelydisablethe Donetlag for the
DMA channel servicingthe receiver, the byte count
shouldbe set to somenumber larger than any packet
that willbe receivq up to 64K. If not usingthe Done
flag,then GSCservicingwouldbe drivenbythe receive
Done (RDN) flagand/or interrupt. RDN is set when
the EOFis detected.Whenusingthe RDN tlag,RFNE
ahouldalso be checkedto insure that all the data has
beenemptiedout of the receiveFIFO.
Thebytecountregisteris usedfor alltransmissionsand
this meansthat all packetsgoingout willhaveto beof
the same lengthor the lengthof the packet to be sent
willhaveto be knownpriorto the start oftransmission.
When using the DMA channels to seMce the GSC
transmitter, there is no practical way to disable the
Done flag. This is because the transmit done fig
(TDN) is setwhenthe transmit FIFO is emptyand the
last messagebit has beentransmitted. But,whenusing
the DMA channelto servicethe tranann‘tier, loads to
the TFIFO continue to occur until the byte count
reaches O.This makes it impossibleto use TDN as a
flagto stopthe DMA transfersto TFIFO. It is possible
to examin
e someother registersor conditions,such as
the current byte count, to deterrmn
“ e whento stop the
DMA transfersto TFIFO,but this isnot recommended
as a wayto seMce the DMA and GSCwhentransmit-
tingbecausefrequentreadingof the DMAregisterswill
cause the effectiveDMA transfer rate to slowdown.
When using the DMA chann~ ini-tion of the
GSCwouldbe exactfythe same as normal exceptthat
TSTAT.O= 1 (DMA),this informsthe GSC that the
DMAchannelsare goingto beusedto servicethe GSC.
AlthoughonlyTSTATis written to, betb the receiver
and transmitter usethis same DMA bit.
The interrupts EGSTE(IEN1.5), GSCtransmit error;
EGSTV (IEN1.3), GSC transmit valid; EGSRE
(IENI.1), GSC receiveerro~ and EGSRV (IEN1.0),
GSCreceivevalid;needto be enabled.TheDMA inter-
rupts are normallynot used when servicingthe GSC
with the DMA channels.To ensurethat the DMA in-
terrupts are not reapondedto is a functionof the user
sotlware and shoufdbe checked by the software to
makesure theyare notenabled.Priorityfortheseinter-
rupts can also be set at this time. Whether to w high
or low priority needsto be decidedby the user. When
respondingto the GSCinterrupts, if a buffer is being
usedto store the GSCinformation,then the DMA reg-
isters used for the bufferwillprobablyneedupdating.
After this initialization,all that needsto be donewhen
the GSC is actuaffygoingto be used is: load the byte
count, set-upthe sourceaddreasesfor the DMA chan-
nel servicingthe transmitter, set-upthe destinationad-
dresses for the DMA channel servicingthe receiver,
and start the DMA transfer. The GSC enable bits
shouldbe set iirst and then the GO bits for the DMA.
This initiates the data transfem.
7-36

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Intel MCS 51 Specifications

General IconGeneral
BrandIntel
ModelMCS 51
CategoryMicrocontrollers
LanguageEnglish

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