in~.
83C152 HARDWAREDESCRIPTION
Thereare four modesin whichthe DMA channel can
operate. These are selectedby the bits DM and TM
(DemandModeand TransferMode)in DCONn:
DM I TM Operating Mode
o 0 AlternateCyclesMode
o
1 BurstMode
1 0 SerialPortDemand Mode
1
1
ErrternalDemandMode
The operatingmodesare describedbelow.
4.1.1 ALTERNATE CYCLE MODE
In AlternateCyclesModethe DMAis initiatedby set-
tingthe GO bit in DCONn.Followingthe instruction
that set the 00 bit, one more instructionis executed,
and then the tirat data byte is transferred from the
sourceaddressto the deadnationaddress.Thensnother
instructionis executed,andthen anotherbyteofdata is
transferred,and so on in this manner.
Each time a data byte is transferred, BCRn (Byte
CountRegister for DMA Channeln) is decremented.
When it reaches OOOOH,on-chiphardware clears the
GO bit and se~ the DONE bit, and the DMA ~m.
The DONEbit tlagsan interrupt.
4.1.2
BURST MODE
BurstModedifTersfromAlternatecycles modeonlyin
that oncethe data transferhas begun,program execu-
tion is entirelysuspendeduntil BCRn reaches OOCKIH,
indicatingthat all databytesthat wereto betransferred
havebeentransferred.The interrupt control hardware
remainsactiveduringthe DMA,sointerrupt tlagsmay
get set, but since programexecutionis suspended,the
interrupts will not be servicedwhile the DMA is in
progress.
4.1.3
SERIAL PORT DEMAND MODE
In thismodethe DMAcanbe usedto servicethe Lad
Serial Channel (LSC) or the Global Serial Channel
(GSC).
In SerialPort
DemandModethe DMA is initiatedby
anyof the followingconditions,if the GO bit is act:
SourceAddress= SBUF
.AND. RI = 1
DestinationAddress= SBUF ,AND. TI = 1
SourceAddress= RFIFO
.AND. RFNE = 1
DestinationAddress= TFIFO .AND. TFNF = 1
Each time one of the above conditions is met, one
DMACycleis executed;that is, onedata byte is trans-
ferred from the source addreas to the destination ad-
dreas.On-chip hardware then clears the tlag (RI, TI,
RFNE, or TFNF) that initiatedthe DMA, and decre-
mentsBCRn.Note that sincethe tlagthat initiated the
DMAis cleared,it willnotgeneratean interrupt unless
DMA servicingis held offor the byte count equals O.
DMAservicingmaybe heldoffwhenalternate cycleis
beingusedor by the statusofthe HOLD/HLDA logic.
In these situationsthe interruptfor the LSCmay occur
beforethe DMA can clear the RI or TI flag. This is
becausethe LSC is seMced accordingto the status of
RI and TI, whetheror not theDMAchannelsare being
usedforthe transferringofdata. The GSCdoesnot use
RFNE or TFNF figs whenusingthe DMA channels
so these do not need to be disabled.When using the
DMA channelsto servicethe LSC it is recommended
that the interrupts (RI and TI) be disabled.If the dec-
remented BCRn is OOOOH,on-chip hardware then
clearsthe GO bit and sets the DONE bit. The DONE
bit flagsan interrupt.
4.1.4
EXTERNAL DEMAND MODE
In External Demand Mode the DMA is initiated by
oneofthe ExternalInterrupt pins,providedthe GO bit
is set. INTOinitiates a Channel O DM& and ~
initiatesa Channel 1 DMA.
If the external interrupt is configuredto be transition-
activata then each l-to-Otransition at the interrupt
pin sets the correspondingexternalinterrupt flag, and
generatesone DMA Cycle.Then,BCRnis decrement-
ed. No more DMA Cyclestake place until another
l-to-Otransition is seenat the externalinterrupt pin. If
the decremented BCRn = OOOOH,on-chip hardware
clearsthe GO bit and setsthe DONE bit. If the exter-
nal interrupt is enabled,it willbe serviced.
If the external interrupt is configuredto be level-acti-
vated,thtmDMA Cyclescommencewhenthe interrupt
pinis pulledlow,and continuefor as longas the pin is
held lowand BCRnis not IXKOH.If BCRn reacheaO
whilethe interruptpin is stilllow,the GObit is clear@
the DONEbit is set, andthe DMAceasea.
If the exter-
nal interrupt is enabled,it willbe serviced.
If the interrupt pin is pulled up before BCRn reaches
OOOOH,then the DMA ceases,but the GO bit is still 1
andtbe DONEbit is still0.An
external interrupt is not
generated in this case, since in
level-activatedmodq
pullingthe pin to a logical1clearsthe interrupt flag.If
the interrupt pin is then pulledlowagain, DMA trans-
fers will continue fkom where they were previously
stopped.
The timing for the DMA Cyclein the tranaition-acti-
vatedmode,or forthe
firstDMACyclein the level-ac-
tivated mode is as follows:If the l-to-Otransition is
7-49
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