To Next Page

To Previous Page

intd.

83C152 HARDWARE DESCRIPTION

If thechannelk configuredto ExternalDeman

d mode,

thenthe tirst if-conditionis not satisfiedbutthe second

one k. In that case the block of statementsfollowing

that if-conditionand delimitedby {...) is executed:if

the demandflag(IEO for channelOand IE1 for chan-

nel 1)is set, the “return 1“ expressionis executedand

the remainderofthe tkwtion is not. If the d

crmmdtlag

is not set,the “return O“expressionis executedand the

remainderof the functionis not.

If the channel is configuredto serial Port Demand

mode,the sourceand destinationaddresses,SARnand

DARn, have to be checked to see which Serial Port

bufferis beingaddressed,and whetherits demandflag

is set.

SARnrefersto the id-bit sourceaddressfor “thischan-

nel.” Notethat the condition

SARn = SBUF

cannotbetrue unlessthe SASand ISAbitsin DCONn

are contlguredto selectSFR space.If SARnisnumeri-

callyequalto theaddressofSBUF(99H),and SASand

ISAare configuredto selectinternal RAM rather than

SFR space, then SARn refers to location99H in the

“upper 128”of internal RAM, not to SBUF.

If thetest forSARn = SBUFirt% andif the flagRI

is set, mode-logic (n) returns as 1and the remainder

of the functionis not executed.Otherwise,execution

proceedsto thenextif-condition,testingDARnagainst

SBUFand T1 against 1.

ThesameconsiderationsregardingSASand ISAin the

SARn teat are now applied to DAS and IDA in the

DARn test. If SFR space isn’tselected,no SerialPort

bufferis beingaddressed.

Notethat ifDMA channeln is configuredto Alternate

Cycleamode,the logicmust examinethe other DCON

“ e if the other channelis

alsocordiguredto Alternate Cyclesmodeand whether

its 00 bit is set. In Figure 4.13, the symbolDCONn

refers to the DCON register for “this channel,” and

DCONmrefersto “the other channel.”

A carefulexaminationof the logicin Figure4.13will

reveal some idiosyncrasies that the user should be

awareof.First,the logicallowssequentialDMAcycles

to be generatedto service RFIFO, but not to service

TFIFO. This idiosyncrasy is due to internal timing

contlicts,and results in each individualDMA cycleto

TFIFO havingto be immediatelyprecededby an In-

struction cycle.The logic disallowsthat there be two

DMAsto TFIFO in a row.

If the useris unawareof this idiosyncrasy,it can cause

problemsinsituationswhereoneDMAchannelis serv-

icingTFIFO andthe other is configuredto a complete-

ly ditTerentmcdeof operation.

For example,considerthe situationwherechannelOis

configuredto serviceTFIFO and channel 1 is config-

uredto AlternateCyclesmode.Then DMAsto TFIFO

willalwaysoverridethe alternate cyclesofchannel1.If

TFIFO needsmore than 1byte it willreceivethem in

precedence overchannel 1,but eachDMAto TFIFO

mustbeprecededbyan Instructioncycle.Thesequemce

of cyclesmightbe:

DMA1 cycle

Instructioncycle

DMA1 CYC1%duringwhichTFNF getsset

Instructioncycle

DMAOcycle

Instructioncycle

DMAOcycle,as a result of whichTFNF getscleared

Instructioncycle

DMA1cycle

Instructioncycle

DMA1cycle

Instruction cycle

.,.

The requirementthat a DMA to TFIFO be preceded

by an Instructioncyclecan result in the normalprece-

denceofchannelOoverchannel1beingthwarted.Con-

sider for

examplethe situationwherechannelOis con-

figuredto serviceTFIFO, andisin the processofdoing

so, and channel 1decidesit wants to do a Burst mode

DMA. The sequenceof eventsmightbe:

Instructioncycle(sets GO bit in DCON1)

Instruction cycle(duringwhichTFNF getsset)

DMAOcycle

DMA1cycle

DMA1 cycle

. ..

DMAI cycle(completeschannel 1burst)

Instructioncycle

DMAOcycle

Instructioncycle

. . .

This sequencebeginswith two Instructioncycles.The

first one

acceswsa DMA registcx(DCONl), andthere-

fore is followed

by another Instruction cycle, which

presumablydoesnot access

a DMA register.After the

seeond Instruction cycle both channels are ready to

generate DMA CyCIS,and Chtllld OOfcoursetakes

preccdcmx. After the DMAOcycle, channel O must

wait for an

Instruction cycle before it can access

TFIFO again.Channel1,beingin Burst mode,doesn’t

havethat restriction,and is thereforegranteda DMA1

cycle. After the fnt DMA1 cyclej channel Ois still

waitingfor an Instmction cycleand channel1still dces

not havethat restriction.TherefoIlowsanotherDMA1

cycle.

7-58

Brand	Intel
Model	MCS 51
Category	Microcontrollers
Language	English

Intel MCS 51 User Manual

Table of Contents

Questions and Answers:

Intel MCS 51 Specifications

Related product manuals