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Intel MCS 51 User Manual
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i~.
M~@-51
PROGRAMMERS
GUIDE
AND
INSTRUCTION
SET
Table
11.
Instruction
Q
Hex
Number
Code
Mnemonic
of
Bytes
Operands
00
01
02
03
04
05
06
07
06
Oe
OA
OB
Oc
OD
OE
OF
10
11
12
13
14
15
16
17
16
19
1A
lB
lC
ID
lE
IF
20
21
22
23
24
25
26
27
28
23
2A
2B
2C
2D
2E
2F
30
31
32
1
2
3
1
1
2
1
1
1
1
1
1
1
1
1
1
3
2
3
1
1
2
1
1
1
1
1
1
1
1
1
1
3
2
1
1
2
2
1
1
1
1
1
1
1
;
:
2
1
NOP
AJMP
WMP
RR
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
INC
JBC
ACALL
LCALL
RRC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
JB
AJMP
RET
RL
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
JNB
ACALL
RETI
code
sddr
codesddr
A
A
dsts
addr
@RO
@Rl
RO
RI
R2
R3
R4
R5
R6
R7
bit
addr,
code
addr
code
addr
codeaddr
A
A
dataaddr
@RO
@Rl
RO
RI
R2
R3
R4
R5
R6
R7
bif
addr,
code
addr
code
addr
A
A,#dats
A,datsaddr
A,@RO
A,@Rl
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
bitaddr,
code
addl
code
addr
i
in
Haxadecirnal
Order
Hex
Number
code
Mnemonic
of
Bytes
operands
33
34
35
36
37
36
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
46
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
5e
59
5A
5B
5C
5D
5E
5F
eo
61
62
63
64
65
1
2
2
1
1
1
1
1
1
1
1
1
1
2
2
2
3
2
2
1
1
1
1
1
1
1
1
1
1
2
2
2
3
2
2
1
1
1
1
1
1
1
1
1
1
2
2
2
3
2
2
RLC
ADDC
ADDC
ADDC
ADDC
ADDC
ADDC
ADDC
ADDC
ADDC
ADDC
ADDC
ADD(2
JC
AJMP
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
ORL
JNC
ACALL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
ANL
JZ
AJMP
XRL
XRL
XRL
XRL
A
A,#data
A,dats
addr
A,@RO
A,@Rl
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
code
addr
code
addr
datsaddr,A
dateaddr,
#data
A,#data
A,dataaddr
A,@RO
A,@Rl
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,Re
A,R7
code
addr
code
addr
dataaddr,A
dataaddr,#data
A,#data
A,datsaddr
A,@RO
A,@Rl
A,RO
A,R1
A,R2
A,R3
A,R4
A,R5
A,R6
A,R7
code
addr
code
addr
datesddr,A
datesddr,#data
A,#data
A,dataaddr
2-25
54
56
Table of Contents
Contents
3
Table of Contents
7
Architectural Overview
9
Introduction
9
Block Diagram
9
Program Memo
9
CHMOS Devices
12
Logical Separation of Program and Data Memory
12
Data Memory
12
Program Memory
13
SFR Space
15
The Mc951 Instruction Set
15
Program Status Word
15
Direct Addressing
16
Register Instructions
16
Addressing Modes
16
Arithmetic Instructions
16
Logical Instructions
18
Data Transfers
18
Internal RAM
18
External RAM
20
Lookup Tables
20
Boolean Instructions
20
Relative Offset
21
Jump
22
Using an External Clock
23
Using the on Chip Oscillator
23
CPU Timing
23
State Sequences
24
Machine Cycles
24
Interrupt Enables
26
Interrupt Priorities
26
Interrupt Structure
26
Simulating a Third Priority Level in Software
27
Additional References
28
Memory Organization
33
Program Memory
33
Data Memory
34
Direct and Indirect Address Area
36
Special Function Registers
38
What Do the Sfrs Contain Just
39
Sfr Memory Map
40
Not Bit Addressable
41
Psw: Program Status Word. Bit Addressable
41
Interrupts
42
Assigning Higher Priority to One or more Interrupts
43
Bit Addressable
43
Priority Within Level
43
Addressable
44
Tcon: Timefvcounter Control Register. Bit Addressable
44
Timer/Counter Control Register
44
Timer Set-Up
45
Timer/Counter
45
T2Con: Timewcounter 2 Control Register. Bit Addressable
47
Generating Baud Rates
49
Scon: Serial Port Control Register Bit Addressable
49
Serial Port in Mode 1
49
Serial Port in Mode O
49
Serial Port Set-Up
49
Serial Port in Mode 3
50
Using Timer/Counter 1 to Generate Baud Rates
50
Flag Settings
51
Instruction Set Summary
51
Instruction Definitions
58
Hardware Description
107
Introduction
111
Specialfunctionregisters
111
Accumulator
113
B Register
113
Data Pointer
113
Stack Pointer
113
Port Structures and Operation
114
PSW Program Status Word Register
114
I/O Configurations
115
Writing to a Port
115
Port Loading and Interfacing
116
Accessing External Memory
117
Read-Modify-Write Feature
117
Timer Oand Timer 1
118
Timer2
120
Serial Interface
121
Multiprocessor Communications
122
Serial Port Control Register
122
Baud Rates
123
Scon
123
Using Timer 1 to Generator Baud Rates
124
Using Timer 2 to Generator Baud Rates
124
More about Mode 0
125
More about Mode 1
125
More about Modes 2 and 3
128
Interrupt Enable Register
131
How Interrupts Are Handled
132
Interrupt Response Timing Diagram
132
IP Interrupt Priority Register
132
Priority Level Structure
132
External Interrupts
133
Response Time
133
Reset
134
Reset Timing
134
Single-Step Operation
134
CHMOS Power Reduction Modes
135
Operatfon
135
Power-On Reset
135
Power-Saving Modes of
135
Idle and Power down Hardware
136
Idle Mode
136
Power Control Register
136
Power down Mode
136
Eprom Versions
137
Exposure to Light
137
One Lock Bit Scheme
137
Two Program Memory Lock Schemes
137
HMOS Versions
138
ONCE Mode
138
ROM Protection
138
The On-Chip Oscillators
138
ESR Vs Frequency
139
Using the HMOS On-Chip Oscillator
139
CHMOS Versions
140
Internal Timing
141
Using the CHMOS On-Chip Oscillator
141
External Data Memory Read Cycle
142
External Program Memory Fetches
142
External Data Memory Write Cycle
143
Port Operation
143
Datamemory
149
Pin Description
149
Special Function Registers
149
Serial Port Registers
150
Timer Registers
150
AUTO-RELOAD (up or down Counter)
152
Capture Mode
152
Timer 2 in Capture Mode
152
Baud Rate Generator
154
Automatic Address Recognitino
155
Framing Error Detection
155
Programmable Clock out
155
Uart
155
Interrupt Priority Structure
157
Interrupt Sources
158
Power down Mode
158
Power off Flag
158
Program Memory Lock
158
Additional References
159
ONCE Mode
159
Data Memory
165
Introduction
165
Program Memory
165
Special Function Registers
166
Port Structures and Operation
169
Writing to a Port
170
Accessing External Memory
172
Port Loading and Interfacing
172
Read-Modify-Write Feature
172
Timer Oand Timer 1
174
Timerwcounters
174
Timer 2
177
Auto Reload Mode
179
Counter
179
T2Mod
179
Timer 2 Auto Reload Mode
179
Baud Rate Generator Mode
180
Programmable Counter Array
180
PCA 16-Bit Timer/Counter
182
Cmod
183
Capture/Compare Modules
184
Ccon
184
PCA Module Modes
185
16-Bit Capture Mode
186
16-Bit Software Timer Mode
186
PCA 16-Bit Capture Mode
186
High Speed Output Mode
187
Watchdog Tmer Mode
187
PCA 8-Bit PWM Mode
188
Pulse Width Modulator Mode
188
Watchdog Timer Mode
188
Serial Interface
189
Automatic Address Recognition
190
Multiprocessor Communications
190
Baud Rates
192
Rates
192
Using Llmer 1 to Generate Baud
192
Using Timer 2 to Generate Baud
192
Interrupts
194
External Interrupts
195
Interrupt Enable
195
PCA Interrupt
195
Priority Level Structure
195
Serial Porl Interrupt
195
Timer Interrupts
195
Reset
199
Response Time
199
Operation
200
Power-On Reset
200
Power-Saving Modes of
200
87C51GB Hardware Description
209
Idlemode
259
Powerdownmode
259
Poweroff Flag
259
On-Chip Oscillator
260
Once Mode
260
Programmemorylock
260
Cpu Timing
262
Comparison of 80C152 and 80C51Bh Features
267
Memoryspace
267
Interruptstructure
275
Globalserialchannel
281
Introduction
281
Localserialchannel
281
Power Downand Idle
281
CSMA/CD Operation
284
SDLC Operation
291
Userdefinedprotocols
298
Usingthe GSC
298
Registerdescriptions
308
Dma Operation
311
DMA Withthe 80C152
311
Serial Backplanevs Network Environment
311
Hold/Holdacknowledge
314
Timingdiagrams
314
Dmaarbitration
319
Summaryof DMA Controlbits
323
Interruptstructure
324
GSC Transmittererror Conditions
326
GSC Receivererrorconditions
327
Glossary
328
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Intel MCS 51 Specifications
General
Brand
Intel
Model
MCS 51
Category
Microcontrollers
Language
English
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