Intel Stratix 10 User Manual

7. Dynamic Reconfiguration
Dynamic reconfiguration is the process of modifying transceiver channels to meet
changing requirements during device operation. You can customize channels by
triggering reconfiguration during device operation or following power-up.
Dynamic reconfiguration is available for Intel Stratix 10 E-Tile Transceiver Native PHY.
Note: In Intel Stratix 10, the Embedded Multi-die Interconnect Bridge (EMIB) can also be
reconfigured in addition to channels using the reconfiguration interface.
Use the reconfiguration interface to dynamically change the transceiver channel
settings and EMIB settings for the following applications.
• Fine tuning signal integrity by adjusting TX analog settings and RX calibration/
adaptation settings
• Enabling or disabling transceiver channel blocks, such as the PRBS generator and
verifier, and loopback modes
• Changing TX/RX settings for multi-data rate support protocols such as CPRI
• Enabling/disabling RS-FEC
The Native PHY IP cores provide the following features that allow dynamic
reconfiguration:
• Reconfiguration interface
• Configuration files
• Multiple reconfiguration profiles
• Embedded reconfiguration streamer
• Altera Debug Master Endpoint (ADME)
• Optional reconfiguration logic
Also see Unsupported Features.
The RS-FEC AVMM interface allows you to reconfigure the RS-FEC block and monitor
status. Further information about how RS-FEC can be changed from one mode to
another will be included in a future user guide release.
Related Information
Unsupported Features on page 121
UG-20056 | 2019.02.04
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English