Intel Stratix 10 - Clock Network Revision History

4.3. Clock Network Revision History
Document
Version
Changes
2019.02.04 Made the following changes:
•
Added instructions for connecting tx_clkout, tx_coreclkin, rx_clkout, and rx_coreclkin.
• Clarified Master-Slave Configuration: Option 2.
• Add recommendations for the QSF Assignments for Reference Clock Pins.
• Changed the maximum reference clock frequency from 500 to 700 and added related instructions to
Reference Clock Pins, and clarified that, although the Intel Stratix 10 E-Tile transceiver reference
clock input pin supports a frequency range of 125 MHz to 700 MHz, the reference clock network
supports a maximum frequency of 500 MHz.
• For 25 Gbps PMA Direct Channel (with FEC) within a Single FEC Block, clarified that TX and RX
Double Width is enabled.
2018.10.08 Made the following changes:
• Updated the "Clock Sharing 25G Ethernet + 24G CPRI" figure.
• Updated the "Clock Sharing 25G Ethernet + 24G CPRI + PMA Direct" figure.
• Added Use Cases and all subsections.
• Removed the "Clocking Sharing Across Multiple IPs" section.
• Added the "E-Tile Channel Placement for a Single 25-Gbps PMA Direct Channel (with FEC) Within a
Single FEC Block" figure.
• Changed the QSF assignment for all parameters in the "QSF Assignments for a Single Reference
Clock Pin (refclk[0])" table.
2018.07.18 Made the following changes:
• Added QSF Assignments for Reference Clock Pins.
• Added Clocking Sharing Across Multiple IPs.
2018.05.15 Made the following changes:
• Updated figure "REFCLK LVPECL Pins" so that refclk_in_B only connects to REFCLK_1.
•
Changed REFCLK to "reference clock" except for references to REFCLK[0-8] and refclk pins.
2018.01.31 Initial release.
4. Clock Network
UG-20056 | 2019.02.04
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10 E-Tile Transceiver PHY User Guide
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