Intel Stratix 10 User Manual

3.1.7. Unused Transceiver Channel
To preserve the performance of unused transceiver channels, Intel Quartus Prime
software can switch the TX/RX channels on and off at a low frequency using an
reference clock. To create clock activity on unused channels by way of a Intel Quartus
Prime Settings File (.qsf) variable, either:
•
Make a global assignment: set_global_assignment -name
PRESERVE_UNUSED_XCVR_CHANNEL ON
•
Use a per-pin assignment: set_instance_assignment -name
PRESERVE_UNUSED_XCVR_CHANNEL ON -to pin_name
For example, if the pin_name is Pin AB44, structure the per-pin assignment with the
following syntax: set_instance_assignment -name
PRESERVE_UNUSED_XCVR_CHANNEL ON -to AB44.
3.2. Physical Coding Sublayer (PCS) Architecture
The Intel Stratix 10 E-Tile PCS is located in the EHIP_LANE block, which includes the
following features:
• 64B/66B encoder/decoder
• Scrambler/descrambler
• Block distribution/block synchronization
• Lane reorder
The PCS features are not available within the Native PHY IP core. Refer to the Intel
Stratix 10 E-Tile Hard IP for Ethernet IP Core User Guide for details about the
EHIP_LANE block.
Related Information
E-Tile Hard IP for Ethernet Intel FPGA IP User Guide
3.3. Reed Solomon Forward Error Correction (RS-FEC) Architecture
The Intel Stratix 10 E-Tile includes a Reed Solomon Forward Error Correction (RS-FEC)
block.
For more basic RS-FEC information, refer to AN 846: Intel Stratix 10 Forward Error
Correction.
The RS-FEC core supports the following standards:
• 100GbE: IEEE 802.3 Clause 91
• 100GbE with KP-FEC: IEEE 802.3 Clause 91
• 128GFC: Fibre Channel Framing and Signaling - 4 (FC-FCS-4) Clause 5.6
• 25GbE: IEEE 802.3 Clause 108
• 32GFC: Fibre Channel Framing and Signaling - 4 (FC-FCS-4) Clause 5.4
3. Intel Stratix 10 E-Tile Transceiver PHY Architecture
UG-20056 | 2019.02.04
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10 E-Tile Transceiver PHY User Guide
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English