Intel Stratix 10 User Manual

7.12. Ports and Parameters
The reconfiguration interface is integrated in the Native PHY instance. Instantiate the
Native PHY IP cores in the IP Parameter Editor by clicking Tools ➤ IP Catalog. You
can define parameters for IP cores by using the IP-core-specific Parameter Editor. To
expose the reconfiguration interface ports, select the Enable dynamic
reconfiguration option when parameterizing the IP core. You can share the
reconfiguration interface among all the channels by turning on Share
reconfiguration interface when parameterizing the IP core. When this option is
enabled, the IP core presents a single reconfiguration interface for the dynamic
reconfiguration of all channels. Address bits [18:0] provide the register address in the
reconfiguration space of the selected channel. The remaining address bits of the
reconfiguration address specify the selected logical channel. For example, if there are
four channels in the Native PHY IP instance, reconfig_address[18:0] specifies
the address and reconfig_address[20:19] are binary encoded to specify the four
channels. For example, 2'b01 in reconfig_address[20:19] specifies logical
channel 1.
The following figure shows the signals available when the Native PHY IP core is
configured for four channels and the Share reconfiguration interface option is
enabled.
Figure 85. Reconfiguration Interface Ports with Shared Native PHY Reconfiguration
Interface
Native PHY IP Core
reconfig_clk
reconfig_reset
reconfig_write
reconfig_read
reconfig_writedata
reconfig_address
reconfig_readdata
reconfig_waitrequest
Table 53. Reconfiguration Interface Ports with Shared Native PHY Reconfiguration
Interface
The reconfiguration interface ports when Share reconfiguration interface is enabled. <N> represents the
number of channels.
Port Name
Direction Clock Domain Description
reconfig_clk
Input N/A The clock frequency is 100
to 162 MHz.
reconfig_reset
Input
reconfig_clk
Resets the AVMM interface.
Asynchronous assertion
and synchronous
deassertion.
reconfig_write
Input
reconfig_clk
Write enable signal. Signal
is active high.
reconfig_read
Input
reconfig_clk
Read enable signal. Signal
is active high.
continued...
7. Dynamic Reconfiguration
UG-20056 | 2019.02.04
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10 E-Tile Transceiver PHY User Guide
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English