Intel Stratix 10 User Manual

Figure 80. Reading from the Reconfiguration Interface
reconfig_clk
reconfig_address
reconfig_read
reconfig_waitrequest
reconfig_readdata
reconfig_write
reconfig_writedata
1
2
3
4
5
1. The master asserts reconfig_address and reconfig_read after the rising edge of reconfig_clk.
2. The slave asserts reconfig_waitrequest, stalling the transfer.
3. The master samples reconfig_waitrequest. Because reconfig_waitrequest is asserted, the cycle becomes a wait state and reconfig_address,
reconfig_read, and reconfig_write remain constant.
4. The slave presents valid reconfig_readdata and deasserts reconfig_waitrequest.
5. The master samples reconfig_waitrequest and reconfig_readdata, completing the transfer.
0x00119
Valid readdata
~17 reconfig_clk cycles
7.5. Writing to the Dynamic Reconfiguration Interface
Writing to the reconfiguration interface of the Transceiver Native PHY IP core changes
the data value at a specific address. All writes to the reconfiguration interface must be
read-modify-writes, because two or more features may share the same
reconfiguration address. You need to monitor the reconfig_waitrequest signal.
7. Dynamic Reconfiguration
UG-20056 | 2019.02.04
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10 E-Tile Transceiver PHY User Guide
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English