Intel Stratix 10 User Manual

Related Information
Intel Stratix 10 Device Datasheet
2.3. Implementing the Transceiver PHY Layer in Intel Stratix 10
Devices Revision History
Document
Version
Changes
2019.02.04 Made the following changes:
• Added PMA Adaptation.
• Changed the maximum TX PMA reference clock frequency from 500 to 700.
• Changed the maximum RX PMA reference clock frequency from 500 to 700.
2018.10.08 Made the following changes:
• Changed the description of the design flow in the "Transceiver Design Flow in the Native PHY IP
Core" section.
• Added new parameters and updated parameter values and descriptions in the "General, Datapath
Options, and Common PMA Options" table.
• Added a note to the description of the TX PMA data rate parameter in the "TX PMA Options" table.
• Added the following sections:
— Reed Solomon Forward Error Correction (RS-FEC) Parameters
— Fibre-channel and CPRI Modes
— 128 GFC Mode
— 25 GbE FEC Direct Mode
— Interlaken Mode
• Changed the description of the Use default TX PMA pre-equalization settings parameter in the
"TX PMA Pre-equlization" table.
• Changed the "PMA Interface Options" figure.
• Updated the "Native PHY IP Core Parameter Editor" figure.
• Updated the "General, Datapath, and Common PMA Options" figure.
• Added the following parameters to the "PMA Interface Options" table:
— Enable tx_enh_pmaif_fifo_almost_full port
— Enable tx_enh_pmaif_fifo_almost_empty port
— Enable tx_enh_pmaif_fifo_overflow port
— Enable tx_enh_pmaif_fifo_underflow port
— Enable rx_pmaif_fifo_underflow port
— Enable rx_enh_pmaif_fifo_overflow port
2018.08.08 Made the following changes:
• Changed the description of the Transceiver mode parameter in the "General, Datapath, and
Common PMA Options" table.
2018.07.18 Made the following changes:
• Added further description about deskew bits to the PMA Direct high data rate PAM4 mode in the
"Parallel Data" table.
• Removed the "Port Diagram" figure.
2018.05.15 Made the following changes:
• Added further description of the PMA Direct modes in the "Transceiver Design Flow in the Native
PHY IP Core" section.
• Updated the "Native PHY IP Core Parameter Editor" figure.
• Added more description to the following parameters in the "Core Interface Parameters" table:
— Enable TX double width transfer
— Enable RX double width transfer
• Added the "Port Information" table.
continued...
2. Implementing the Transceiver PHY Layer in Intel Stratix 10 Devices
UG-20056 | 2019.02.04
Intel
®
Stratix
®
10 E-Tile Transceiver PHY User Guide
Send Feedback
54

Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English