Intel Stratix 10 User Manual

Return Value {0x89[7:0],0x88[7:0]}
0x0017 for successful error counter reset
9.2.13. 0x0018: Status/Debug Register
Attribute Code
0x0018
Description
Sets up which status/debug register to be used for subsequent read/write operations.
• {0x85[7:0],0x84[7:0]}:
— 0x0000: Select 80b-wide TX data to be written 10b at a time starting from the
LSB by asserting PMA attribute code 0x19 (assert the PMA attribute code eight
times)
• {0x85[7:0],0x84[7:0]}:
— 0x0001: Select 80b-wide RX data to be written 10b at a time starting from the
LSB by asserting PMA attribute code 0x19 (assert the PMA attribute code eight
times)
• {0x85[7:0],0x84[7:0]}:
— 0x0002: Select 30b-wide error timer to be read 16b at a time starting from
the LSB by asserting PMA attribute code 0x1A (assert the PMA attribute code
two times)
• {0x85[7:0],0x84[7:0]}:
— 0x0003: Select 32b-wide error counter to be read 16b at a time starting from
the LSB by asserting PMA attribute code 0x1A (assert the PMA attribute code
two times)
• {0x85[7:0],0x84[7:0]}:
— 0x0004: Select 80b-wide recovered RX data to be read 10b at a time starting
from the LSB by asserting PMA attribute code 0x19 (assert the PMA attribute
code eight times)
PMA Can Be Running While Updating PMA Attribute?
Yes
Return Value {0x89[7:0],0x88[7:0]}
0x0018
9.2.14. 0x0019: Status/Debug Register Next Write Field
Attribute Code
0x0019
Description
Writes the next field of a status/debug register. 0x85[7:0], 0x84[7:0] represent the
value to be written.
9. Register Map
UG-20056 | 2019.02.04
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10 E-Tile Transceiver PHY User Guide
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English