Intel Stratix 10 User Manual

E-Tile Native
PHY Mode
TX/RX PMA
Interface
Width
Enable TX/RX
double width
transfer
Valid Parallel Data Note
PMA Direct 16 Yes Data [55:40]
Data [15:0]
Data [55:40] is the first data group. Data
[15:0] is the second data group.
PMA Direct 20 Yes Data [59:40]
Data [19:0]
Data [59:40] is the first data group. Data
[19:0] is the second data group.
PMA Direct 32 Yes Data [71:40]
Data [31:0]
Data [71:40] is the first data group. Data
[31:0] is the second data group.
PMA Direct high
data rate PAM4
64 No Data [111:80]
Data [31:0]
Data [31:0] is the lower bits data. Data
[111:80] is the upper bits data.
PMA Direct high
data rate PAM4
64 Yes Data [151:120]
Data [71:40]
Data [111:80]
Data [31:0]
Data [151:120] and Data [71:40] are the first
data group. In this group, Data [71:40] is the
lower bits data. Data [151:120] is the upper
bits data.
Data [111:80] and Data [31:0] are the second
data group. In this group, Data [31:0] is the
lower bits data. Data [111:80] is the upper
bits data.
For single width transfer, Data[33] and Data[113] are deskew bits (deskew pulse). For
double width transfer, Data[33], Data[73], Data[113], and Data[153] are deskew bits
(deskew pulse). You must detect the number of parallel clock cycle skew by using the
deskew bit pulses.
For the extra data bit's detailed usage, please contact local support.
2.2.10. PLL Mode
PLL mode is one configuration of the E-Tile Transceiver Native PHY IP. It configures the
E-Tile transceiver as a PLL. It does not support dynamic reconfiguring between PLL
and other Transceiver Configuration Rules.
2. Implementing the Transceiver PHY Layer in Intel Stratix 10 Devices
UG-20056 | 2019.02.04
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10 E-Tile Transceiver PHY User Guide
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English