Intel Stratix 10 User Manual

Figure 8. GXE Channel Usage Example: Channels Running at Data Rates < 30 Gbps
PAM4/NRZ PMA Direct Mode without RS-FEC
1.4.3. Reference Clocks
Intel Stratix 10 E-Tile transceivers include a reference clock network for clocking
flexibility and channel bonding. There are up to nine low-voltage positive/pseudo
emitter-coupled logic (LVPECL) reference clock pins on the tile, which are dynamically
selectable through two inputs, refclk_in_A and refclk_in_B, to drive the
transmitter/receiver. You can configure the pins as either 2.5-V LVPECL compliant or
3.3-V LVPECL tolerant. Intel recommends that you use the default setting, which
includes source termination at 2.5 V and AC coupling caps. The Intel Stratix 10 Device
Datasheet provides the electrical characteristics under the E-Tile section. Additional
important electrical information is available in the Intel Stratix 10 GX, MX, and SX
Device Family Pin Connection Guidelines.
Table 5. Key Reference Clock Considerations
Consideration Description
Power The reference clock pins support only the low-voltage positive/pseudo emitter-coupled
logic (LVPECL) standard. The pins are internally terminated to 2.5 V by default, but are
tolerant to 3.3 V as well. You can disable the termination and place external termination
continued...
1. Intel
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Stratix
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10 E-Tile Transceiver PHY Overview
UG-20056 | 2019.02.04
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Intel
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10 E-Tile Transceiver PHY User Guide
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English