Intel Stratix 10 User Manual

2.2.2.4. RX PMA Optional Ports
Table 12. RX PMA Optional Ports
Parameter Value Description
Enable
rx_is_lockedtodata
port
On/Off
Enables the optional rx_is_lockedtodata status output port. This signal
indicates that the RX CDR is currently in lock to data mode, or is attempting
to lock to the incoming data stream. This is an asynchronous output signal,
and is also available as part of the E-Tile Native PHY register space.
Enable
rx_pma_elecidle
port
On/Off
Enables the optional rx_pma_elecidle status port, which is used for the
idle.
2.2.3. Core Interface Options
These Native PHY IP core parameters allow you to customize the transceiver-to-core
interface.
2. Implementing the Transceiver PHY Layer in Intel Stratix 10 Devices
UG-20056 | 2019.02.04
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10 E-Tile Transceiver PHY User Guide
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English