Intel Stratix 10 - Page 34

Figure 19. Core Interface Options
2.2.3.1. Core Interface Parameters
The core interface is the interface between the transceiver EMIB and the FPGA core
EMIB. You can use these options to customize the core interface.
Based on the transceiver configuration rule you select, the Native PHY IP core
Parameter Editor reports error or warning messages if your settings violate the
protocol standard.
2. Implementing the Transceiver PHY Layer in Intel Stratix 10 Devices
UG-20056 | 2019.02.04
Intel
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Stratix
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10 E-Tile Transceiver PHY User Guide
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