Intel Stratix 10 User Manual

6.5.2. Manual Reset Mode
In manual mode, all ports are exposed to provide flexible control. Follow the reset
sequence for RX and TX modes to send reset requests.
Note: The manual reset mode is required if fractured RS-FEC is used.
Table 47. Native PHY IP Ports With Manual Mode Enabled
Port Direction Description
rx_reset_req
Input Request to Master TRS to schedule RX reset
rx_reset_ack
Output
Valid window for you to assert/deassert rx_aib_reset, rx_pmaif_reset,
rx_rsfec_reset
rx_aib_reset
Input Reset RX EMIB datapath
rx_pmaif_reset
Input Reset RX PMA digital logic
rx_rsfec_reset
Input Reset RX RS-FEC datapath
rx_transfer_ready
Output Output from the Native PHY IP core indicating the RX EMIB datapath is ready
rx_pma_ready
Output Output from the PMA indicating the PMA is ready. This must be asserted before
asserting or deasserting any RX resets.
rx_is_lockedtodata
Output Output from the PMA indicating the CDR has locked to the incoming serial data
tx_reset_req
Input Request to Master TRS to schedule TX reset
tx_reset_ack
Output
Valid window to assert or deassert tx_aib_reset, tx_pmaif_reset,
tx_rsfec_reset, rsfec_reset
rsfec_reset
Input Reset all RS-FEC logic
tx_aib_reset
Input Reset TX EMIB datapath
tx_pmaif_reset
Input Reset TX PMA digital logic
tx_rsfec_reset
Input Reset TX RS-FEC datapath
tx_transfer_ready
Output Output from the Native PHY IP core indicating the TX EMIB datapath is ready
tx_pma_ready
Output Output from the PMA indicating the PMA is ready. This must be asserted before
asserting or deasserting any TX resets.
The reset, rx_ready, and tx_ready ports do not appear in manual reset mode.
6. Resetting Transceiver Channels
UG-20056 | 2019.02.04
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10 E-Tile Transceiver PHY User Guide
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English