Intel Stratix 10 User Manual

Figure 64. Manual Reset Mode
E-Tile Native PHY IP
Reset Controller
RS-FEC
EMIB
PMA Interface
Master TRS
Request
tx_reset_req
tx_reset_ack
Acknowledgement
TX
RX
PMA
rx_reset_req
rx_reset_ack
rsfec_reset
tx_rsfec_reset
rx_rsfec_reset
tx_aib_reset
rx_aib_reset
tx_transfer_ready
rx_transfer_ready
tx_pma_ready
rx_pma_ready
tx_pmaif_reset
rx_pmaif_reset
You assert the tx_reset_req or rx_reset_req ports to start the digital reset
process. You need to assert tx_reset_req or rx_reset_req every time you want
to assert or deassert reset signals. You can assert req ports on multiple channels at
the same time. The Local TRS and Master TRS round robin and stagger the resets.
However:
• If you use the RS-FEC block and want to reset both the TX and RX, you must
complete the TX reset on a specific channel before resetting the RX on that
channel.
•
You must ensure that the tx_pma_ready output is asserted before asserting the
tx_reset_req.
•
You must ensure that the rx_pma_ready output is asserted before asserting the
rx_reset_req.
•
You must monitor rx_is_lockedtodata.
•
After rx_lockedtodata stays high for 180 µs, you may deassert the RX digital
resets.
The following use model is supported:
1.
You assert multiple reset_req. The Local TRS forwards the reset_req signal to
the Master TRS.
2.
The Master TRS selects one of the reset_req and waits 200 ns before asserting
the reset_ack output.
3. You assert the resets on the EMIB, RS-FEC, and PMA interfaces. See Figure 66 on
page 109 through Figure 71 on page 112 for TX and RX reset sequences.
4.
You deassert the reset_req signal after resetting the blocks.
5.
The Master TRS sees the deasserted reset_req and deasserts the reset_ack
output.
6. Resetting Transceiver Channels
UG-20056 | 2019.02.04
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10 E-Tile Transceiver PHY User Guide
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English