Intel Stratix 10 User Manual

Bit Name Description SW Access
HW Access
Protection
Reset
Set when the number of symbol errors in a window of 8192 consecutive codewords
has exceeded 417 with RS528 and 6380 with RS544.
If RSFEC_LANE_CFG.indic_byp = 1, then sync header errors will be generated
towards the PCS layer for a period of 60ms to 75ms.
W1S
-
3 am_5bad RX was locked (and aligned if RSFEC_CORE_CFG.frac = none) but 5 consecutive
alignment/codeword markers were not valid.
Restarts the synchronization.
W1C
W1S
-
0x0
2 fec_3bad RX was locked (and aligned if RSFEC_CORE_CFG.frac = none) but 3 consecutive FEC
codewords could not be corrected.
Restarts the synchronization.
W1C
W1S
-
0x0
1 not_locked RX lane not locked.
Not locked to alignment/codeword markers (100GE/128GFC/25GE) or to FEC
codewords (32GFC).
One entry per physical lane, regardless of RSFEC_CORE_CFG.frac.
W1C
W1S
-
0x0
0 sf Incoming signal fail (transceiver unable to lock to signal).
One entry per physical lane, regardless of RSFEC_CORE_CFG.frac.
W1C
W1S
-
0x0
9.5.14. rsfec_lane_rx_inten
Register Name Description Address Addressing Mode
rsfec_lane_rx_inten_
0
RS-FEC per lane RX status hold interrupt -
set to 1 to enable rsfec_lane_rx lane
interrupt
0x170 32-bits
rsfec_lane_rx_inten_
1
0x174
rsfec_lane_rx_inten_
2
0x178
rsfec_lane_rx_inten_
3
0x17C
The reset values in this table represents register values after a reset has completed.
Bit
Name Description SW Access
HW Access
Protection
Reset
6 uncorr_cw Set when a FEC code word could not be corrected due to too many errors. RW
RO
-
0x0
5 corr_cw Set when a FEC code word had one or more errors that were corrected. RW
RO
-
0x0
4 hi_ser High symbol error rate.
Set when the number of symbol errors in a window of 8192 consecutive codewords
has exceeded 417 with RS528 and 6380 with RS544.
If RSFEC_LANE_CFG.indic_byp = 1, then sync header errors will be generated
towards the PCS layer for a period of 60ms to 75ms.
RW
RO
-
0x0
3 am_5bad RX was locked (and aligned if RSFEC_CORE_CFG.frac = none) but 5 consecutive
alignment/codeword markers were not valid.
RW
RO
0x0
continued...
9. Register Map
UG-20056 | 2019.02.04
Intel
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Stratix
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10 E-Tile Transceiver PHY User Guide
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English