Intel Stratix 10 User Manual

4.2.5. PMA Direct 10.3125 Gbps x 4
Connect tx_clkout (257.8125 MHz) of each individual channel to tx_coreclkin
and connect rx_clkout (257.8125 MHz) to rx_coreclkin. If you use any other
source for tx_coreclkin/rx_coreclkin, make sure tx_coreclkin and
rx_coreclkin have 0 PPM difference with tx_clkout and rx_clkout, respectively.
The clocking scheme in this use case is the same as Figure 52 on page 91.
4.2.6. PMA Direct 100GE Gbps (25 Gbps x 4 per lane) (FEC On)
This use case is implemented in the case of multi-lane protocols like 100GbE, for
example. This uses four transceiver lanes of 25 Gbps each, where all four lanes must
use the same FEC block. FEC is clocked by one of the four channels and you can
configure this in the Native PHY IP core Parameter Editor. There is an inherent
dependency between channels in this configuration. However, for applications like 100
GbE, dependency is acceptable and sometimes required. For each of the four channels
with Core Interface FIFOs in Phase Compensation mode, connect tx_clkout (402.83
MHz) to tx_coreclkin, and connect rx_clkout (402.83 MHz) to rx_coreclkin.
If you use any other source for tx_coreclkin or rx_coreclkin, make sure
tx_coreclkin and rx_coreclkin have 0 PPM difference with the tx_clkout and
rx_clkout, respectively.
4. Clock Network
UG-20056 | 2019.02.04
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10 E-Tile Transceiver PHY User Guide
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English