Intel Stratix 10 User Manual

a. Write 0x84[7:0] = 0x00.
b. Write 0x85[7:0] = 0x00.
c. Write 0x86[7:0] = 0x1A.
d. Write 0x87[7:0] = 0x00.
e. Write 0x90[0] = 1'b1.
f. Read 0x8A[7]. It should be 1.
g. Read 0x8B[0] until it changes to 0.
h. Write 0x8A[7] to 1'b1 to clear the 0x8A[7] value.
i. Read 0x88[7:0]. This represents bits [7:0] of the error counter.
j. Read 0x89[7:0]. This represents bits [15:8] of the error counter.
10. Read the upper 16 bits of the error counter.
a. Write 0x84[7:0] = 0x00.
b. Write 0x85[7:0] = 0x00.
c. Write 0x86[7:0] = 0x1a.
d. Write 0x87[7:0] = 0x00.
e. Write 0x90[0] = 1'b1.
f. Read 0x8A[7]. It should be 1.
g. Read 0x8B[0] until it changes to 0.
h. Write 0x8A[7] to 1'b1 to clear the 0x8A[7] value.
i. Read 0x88[7:0]. This represents bits [23:16] of the error counter.
j. Read 0x89[7:0]. This represents bits [31:24] of the error counter.
Note: During PMA performance verification testing, with continuous adaptation running in
background, error bits cannot be accumulated to calculate BER because the Hard
PRBS error counter is in a busy state. You can read errors during continuous
adaptation by implementing a soft PRBS generator and verifier. Errors can be
accumulated in hard PRBS error counter after stopping the continuous adaptation.
8.3. PMA Error Injection
Inject either a single error or a burst of errors on the TX driver output using PMA
attribute codes. This switches the internal TX error injection signal on and off for the
number of bits requested.
8. Dynamic Reconfiguration Examples
UG-20056 | 2019.02.04
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10 E-Tile Transceiver PHY User Guide
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English