Bit Name Description SW Access
HW Access
Protection
Reset
Restarts the synchronization. -
2 fec_3bad RX was locked (and aligned if RSFEC_CORE_CFG.frac = none) but 3 consecutive FEC
codewords could not be corrected.
Restarts the synchronization.
RW
RO
-
0x0
1 not_locked RX lane not locked.
Not locked to alignment/codeword markers (100GE/128GFC/25GE) or to FEC
codewords (32GFC).
One entry per physical lane, regardless of RSFEC_CORE_CFG.frac.
RW
RO
-
0x0
0 sf Incoming signal fail (transceiver unable to lock to signal).
One entry per physical lane, regardless of RSFEC_CORE_CFG.frac.
RW
RO
-
0x0
9.5.15. rsfec_lanes_rx_stat
Description Address Addressing Mode
RS-FEC combined lanes RX status 0x180 32-bits
The reset values in this table represents register values after a reset has completed.
Bit Name Description SW Access
HW Access
Protection
Reset
1 not_deskew All RX lanes locked but the alignment markers were not unique or the skew was too
large.
This is an event signal, so use .not_align above instead to determine the alignment
state.
Restarts the synchronization.
Only applicable when RSFEC_CORE_CFG.frac = none (100GE/128GFC).
RO
WO
-
0x0
0 not_align RX lanes not aligned (state).
Incoming signal fail, RX lanes not all locked, alignment markers not unique or skew
too large.
Only applicable when RSFEC_CORE_CFG.frac = none (100GE/128GFC).
RO
WO
-
0x0
9.5.16. rsfec_lanes_rx_hold
Description
Address Addressing Mode
RS-FEC combined lanes RX hold status 0x188 32-bits
The reset values in this table represents register values after a reset has completed.
Bit
Name Description SW Access
HW Access
Protection
Reset
1 not_deskew All RX lanes locked but the alignment markers were not unique or the skew was too
large.
This is an event signal, so use .not_align above instead to determine the alignment
state.
Restarts the synchronization.
W1C
W1S
-
0x0
continued...
9. Register Map
UG-20056 | 2019.02.04
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10 E-Tile Transceiver PHY User Guide
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