Intel Stratix 10 User Manual

9.5.19. rsfec_ln_skew_rx
Register Name Description Address Addressing Mode
rsfec_ln_skew_rx_0 RS-FEC FEC lane skew 0x1B0 32-bits
rsfec_ln_skew_rx_1 0x1B4
rsfec_ln_skew_rx_2 0x1B8
rsfec_ln_skew_rx_3 0x1BC
The reset values in this table represents register values after a reset has completed.
Bit Name Description SW Access
HW Access
Protection
Reset
6:0 skew Lane skew value (unit is 80 bits).
Only valid when the RX lanes are aligned.
Only applicable when RSFEC_CORE_CFG.frac = none (100GE/128GFC).
RO
WO
-
0x00
9.5.20. rsfec_cw_pos_rx
Register Name Description Address Addressing Mode
rsfec_cw_pos_rx_0 RS-FEC codeword bit position on RX 0x1C0 32-bits
rsfec_cw_pos_rx_1 0x1C4
rsfec_cw_pos_rx_2 0x1C8
rsfec_cw_pos_rx_3 0x1CC
The reset values in this table represents register values after a reset has completed.
Bit
Name Description SW Access
HW Access
Protection
Reset
12:0 num Bit number of first bit in FEC codeword.
Only intended for debug of deterministic latency.
RO
WO
-
0x0000
9.5.21. rsfec_core_ecc_hold
Description
Address Addressing Mode
RS-FEC SRAM ECC status hold 0x1D0 32-bits
The reset values in this table represents register values after a reset has completed.
Bit
Name Description SW Access
HW Access
Protection
Reset
15:8 mbe SRAM ECC uncorrectable error detected.
Same bit ordering as for .sbe above.
W1C
WO1S
-
0x00
7:0 sbe SRAM ECC correctable (single bit) error detected. W1C 0x00
continued...
9. Register Map
UG-20056 | 2019.02.04
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10 E-Tile Transceiver PHY User Guide
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Intel Stratix 10 Specifications

General

Brand	Intel
Model	Stratix 10
Category	Control Unit
Language	English